Lpc4322/rt1170 gcc #9
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Signed-off-by: Alex Yang <alex.yang@nxp.com> Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Compiling ../../../source/family/freescale/target_reset_mimxrt.c
In file included from ../../../source/target/target_config.h:29,
from ../../../source/family/freescale/target_reset_mimxrt.c:50:
../../../source/daplink/util.h: In function 'validate_bin_nvic':
../../../source/daplink/util.h:70:24: error: invalid storage class for function 'util_div_round_up'
70 | inline static uint32_t util_div_round_up(uint32_t dividen, uint32_t divisor)
| ^~~~~~~~~~~~~~~~~
../../../source/daplink/util.h:75:26: error: invalid storage class for function 'util_div_round_down'
75 | __STATIC_INLINE uint32_t util_div_round_down(uint32_t dividen, uint32_t divisor)
| ^~~~~~~~~~~~~~~~~~~
../../../source/daplink/util.h:80:26: error: invalid storage class for function 'util_div_round'
80 | __STATIC_INLINE uint32_t util_div_round(uint32_t dividen, uint32_t divisor)
| ^~~~~~~~~~~~~~
make: *** [Makefile:213: build/target_reset_mimxrt.o] Error 1
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
The stack and heap have to reside in m_data. The largest symbols (.bss.TraceBuf, .bss.sector_buf, .bss.DAP_Cmd_queue) are explicitly placed in m_data_2. Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
this provides definitions needed by GetClockFreq()
It provides GetClockFreq() which is needed by USART_LPC43xx.
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
This way, one can set SWO_UART from the target's yaml. Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
From DAP_config.h: This value is used to calculate the SWD/JTAG clock speed that is generated with I/O Port write operations in the Debug Unit by a Cortex-M MCU. If the Debug Unit uses a Cortex-M0+ processor with high-speed peripheral I/O then only 1 processor cycle might be required. Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Collaborator
|
Hi @groleo, I am thinking about creating a PR to DAPLink:experimental_compilers with only some of the LPC4322 changes. It already works on GCC on this branch. In order, I am interested:
The MIMXRT1170 could be a later PR. I will probably have a several questions. |
Author
|
Hi, I've left the mimxrt1170 bits out : ARMmbed#813 |
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