soc: riscv: esp32c6: add RISCV_PMP and USERSPACE support

[sylvioalves]

Summary

• Add infrastructure for SoC-specific PMP regions via iterable sections
• Enable PMP and userspace support for ESP32-C6

Description

This PR introduces a mechanism for RISC-V SoCs to define custom PMP regions
that are automatically programmed during PMP initialization. This is needed
for SoCs like ESP32-C6 where code execution spans multiple memory regions
(SoC ROM, IRAM, flash) that all need PMP coverage for userspace to work.

Changes

arch/riscv (generic infrastructure):

• Add struct pmp_soc_region and PMP_SOC_REGION_DEFINE() macro to pmp.h
• Add linker snippet pmp.ld for iterable section collection
• Iterate over SoC-defined regions in z_riscv_pmp_init()

soc/espressif/esp32c6:

• Define PMP regions for SoC ROM (0x40000000) and IRAM text section
• Enable PMP_NO_LOCK_GLOBAL (required because PMP init runs from IRAM
  while the main rom region is in flash-mapped memory)
• Add userspace linker support in default.ld
• Add soc_rom device tree node for ROM region address/size

[sylvioalves]

This PR can be split in 2 if mandatory to make it clear about riscv arch changes and soc itself. However, combining it here gives a better view of the SoC dependency. I gently ask the riscv maintainers to check the PMP memory changes and suggest alternatives if needed. Thanks!

[sonarqubecloud]

Quality Gate passed

Issues
1 New issue
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

[fkokosinski]

arch/riscv (generic infrastructure):

Question: have you considered using memory region with attributes? See e.g. here: https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay

[sylvioalves]

arch/riscv (generic infrastructure):

Question: have you considered using memory region with attributes? See e.g. here: https://github.com/zephyrproject-rtos/zephyr/blob/main/tests/arch/riscv/pmp/mem-attr-entries/memattr_mapping.overlay

Hi, that was my initial approach before adding the custom PMP region. See, IRAM and DRAM share the same physical memory region (internal SRAM), but need different PMP permissions:

1. IRAM text (has kernel code) needs R+X (read + execute, no write)
2. DRAM data needs R+W (read + write, no execute)

With memory-attr overlays, you define static memory regions in DTS, but ESP32-C6's IRAM text section boundaries (_iram_text_start, _iram_text_end) are only known at link time - they depend on what code gets placed in IRAM.

The other way around is to add the whole dram/iram with memory attributes, but that isn't correct. Thoughts?