This repository extends the Microchip PolarFire SoC Icicle Kit Reference Design by implementing a Mi-V RISC-V lockstep solution.
The original reference design by Microchip can be found here: PolarFire® SoC Icicle Kit Reference Design Generation Tcl Scripts - Libero® SoC v2024.2+
This configuration builds upon the official Microchip Icicle Kit Reference Design for the PolarFire SoC by integrating a lockstep execution mechanism based on the Mi-V RISC-V architecture. The lockstep solution enhances fault tolerance by duplicating and synchronizing instruction execution across two Mi-V processor cores.
For full details of the original design, please consult the official Microchip repository linked above.
-
Mi-V Lockstep Implementation:
Implementation of a Mi-V Lockstep subsystem integrated into the existing FPGA fabric. The subsystem features a dual-core lockstep architecture based on Mi-V RISC-V cores, complemented by a set of pre-built and custom IP blocks required to support and enable the correct operation of the solution. -
New Project Generation Argument:
Extended the Tcl generation scripts (MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl) to accept a new command-line argument (MIV_LOCKSTEP) enabling easy inclusion of the lockstep features during project setup. -
Design Constraints and Integration:
Updated FPGA constraints to accommodate additional clocks, resets, and I/O signals required by the lockstep modules.
To generate and build the design with the Mi-V lockstep configuration enabled, follow these steps:
1. Configure the Icicle Kit Board
Refer to MPFS Icicle Kit Embedded Software User Guide for jumper settings.
Verify that the power source is properly connected, and ensure reliable USB_JTAG and USB_UART connections before proceeding.
2. Obtain the project files
Clone or download the project repository.
3. Launch Microchip Libero® SoC Design Suite (version v2024.2 or later recommended)
4. Execute the design generation Tcl script
Open the Execute Script dialog by pressing Ctrl+U or by selecting Execute Script from the Tool tab in Libero®.
Run the script: MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl -arg MIV_LOCKSTEP
Note: The (MIV_LOCKSTEP) argument must be used exclusively and cannot be combined with other project generation arguments (i.e., those listed in Table 1 of the official Microchip Icicle Kit Reference Design repository: PolarFire® SoC Icicle Kit Reference Design Generation Tcl Scripts - Libero® SoC v2024.2+). For example, you cannot pass both I2C_LOOPBACK and MIV_LOCKSTEP simultaneously. This behavior is consistent with the official design guidelines of Microchip. For generating the design without the lockstep configuration, omit the (MIV_LOCKSTEP) argument and follow the original Microchip instructions.
5. Run the SoC Design flow
Proceed with executing the full SoC design flow as guided by the tool.
Note: When running the design flow, double-click Configure Design Initialization Data and Memories in the Design Flow tab. Then, in the Fabric RAMs tab, locate and double-click MIV_LOCKSTEP_SUBSYSTEM/PF_SRAM_AHBL_AXI_C0_0 from the list of logical instances. In the Edit Fabric RAM Initialization Client window, ensure that the Storage Type is set to sNVM, and that the Import Memory File field points to the .hex application file located in the repository miv-rv32-lockstep. Finally, save and apply the changes. This configuration ensures that the system controller initializes the RAM instance with the sNVM client’s content during power-up.
Mi-V Lockstep Architecture
The Mi-V Lockstep application demonstrates a fault-tolerant processing system based on the Mi-V RISC-V architecture. It integrates two identical Mi-V RISC-V processors operating in lockstep mode, where both cores execute the same instructions cycle-by-cycle with a fixed two-clock delay between them. A dedicated comparison module continuously monitors the outputs of both processors to detect any mismatches. If a difference occurs, the system flags the error, activating an onboard LED to indicate the fault condition. As part of its recovery mechanism, the system automatically resets after a predefined period following fault detection, restoring normal operation and maintaining overall system reliability.
Operation and Board Simulation
The Mi-V Lockstep system operation can be demonstrated and tested directly on the development board through a fault simulation setup.
To simulate a fault condition, Button 4 is used to generate an interrupt on one of the processors. This event causes the two Mi-V cores to diverge in their behavior, triggering the fault detection mechanism. Conversely, Button 3 is used to manually reset the system.
LED indicators are used to visualize the system’s behavior during normal operation and fault conditions. At the application level, an onboard LED continuously toggles on and off as part of the program executed simultaneously by both Mi-V processors. This LED reflects a logical AND operation between the outputs of the two cores, confirming synchronized execution under normal conditions.
When a fault is simulated, a pair of LEDs (one per Mi-V core) turn on while the interrupt generated by Button 4 is active. Additionally, another LED lights up when a mismatch between the two Mi-V cores is detected, indicating a fault in the system.
This setup provides a clear and interactive way to visualize the lockstep mechanism, error detection, and system recovery directly on the hardware platform.
Microchip Mi-V RISC-V Application Note: PolarFire FPGA Building a Mi-V Processor Subsystem AN4997
Microchip Lockstep Application Note: RT PolarFire Lockstep Processor AN4228
Libero® SoC Design Suite: Libero SoC Design Suite Help Documentation