Fearless hardware design
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Aug 20, 2025 - Verilog
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hardware-accelerator
Here are 39 public repositories matching this topic...
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
deep-neural-networks accelerator convolutional-neural-networks sparse-matrix gemm noc im2col hardware-accelerator eyeriss-v2
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Jul 22, 2025 - Verilog
Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration
pytorch embedded-systems computational-neuroscience verilog xilinx spiking-neural-networks vivado pynq verilog-hdl snn neuromorphic-computing leaky-integrate-and-fire-neuron lif-neuron spiking-neural-network vitis hardware-accelerator lif-model
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May 1, 2026 - VHDL
SneakySnake:snake: is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.o…
fpga gpu smith-waterman needleman-wunsch sequence-alignment long-reads minimap2 short-reads hardware-accelerator sequence-aligner edlib pre-alignment-filtering wavefront-alignment
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Mar 31, 2023 - VHDL
NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
machine-learning acceleration simulator deep-learning memory model accelerator architecture modeling hierarchy cycle-accurate deep-neural-network npu hardware-accelerator full-system value-aware functional-simulation timing-simulation
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Jan 2, 2025 - C++
audio/video toolkit based FFmpeg 6.x, 7.x supported for multimedia with Hardware Acceleration.
audio video ffmpeg multimedia media audio-streaming video-streaming mux hardware-acceleration encoder-decoder muxer hardware-accelerator
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Mar 24, 2026 - Rust
Open source RTL simulation acceleration on commodity hardware
hardware simulation rtl verilog systemverilog hardware-acceleration hardware-accelerator hardware-accelerators
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Apr 13, 2023 - Python
Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data
open-hardware dnn edge-computing tcn continual-learning few-shot-learning hardware-accelerator ai-accelerator
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Mar 5, 2026 - Python
NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators
machine-learning acceleration deep-learning mapping optimization accelerator scheduler architecture scheduling optimizer dataflow hierarchy deep-neural-network hardware-accelerator
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Mar 20, 2025 - C++
GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and computational overheads of genome sequence analysis by exploiting low-cost and accurate in-storage filters. Described in the ASPLOS 2022 paper by Mansouri Ghiasi et al. at https://people.inf.ethz.ch/omutlu/pub/GenS…
ftl ssd sequence-alignment read-mapping long-reads hardware-accelerator near-data-processing pre-alignment-filtering in-storage-processing exact-matching
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Apr 6, 2022 - C
Bare-metal FPGA implementation of the pccx NPU for LLM inference on Kria KV260: SystemVerilog RTL, W4A8 quantization, GEMM/GEMV datapaths, KV-cache scheduling, and driver code.
asic fpga parallel-computing transformer xilinx isa systemverilog quantization gemma xilinx-fpga inference-engine npu edge-ai hardware-accelerator kv260 llm gemma3n gemma4
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May 1, 2026 - SystemVerilog
Garuda: CVXIF coprocessor optimizing batch-1 attention microkernels with 7.5-9× lower p99 latency. RISC-V INT8 MAC accelerator for transformer inference.
machine-learning neural-network inference simd low-latency systemverilog attention-mechanism risc-v int8 systemverilog-hdl systolic-arrays edge-ai hardware-accelerator int8-quantization cva6 custom-instructions ai-hardware cvxif
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Jan 23, 2026 - SystemVerilog
NPUWattch: ML-based Power, Area, and Timing Modeling for Neural Accelerators
machine-learning library acceleration simulator simulation model accelerator architecture modeling timing estimation power estimator area pdk npu neural-accelerator hardware-accelerator post-layout
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Apr 13, 2026 - HCL
Hardware accelerator for 2D convolution using an 8×8 weight-stationary systolic array with split-kernel support, dual-port SRAM architecture, and DMA-based streaming
fpga verilog sram convolution vlsi dma digital-design systolic-arrays rtl-design hardware-accelerator systolic-array
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Feb 8, 2026 - Verilog
PCCX is an open NPU architecture for memory-bound Transformer inference on edge FPGAs, focused on GEMM/GEMV, KV-cache, W4A8 quantization, and custom ISA scheduling.
fpga neural-network parallel-computing transformer rtl isa deeplearning systemverilog computer-architecture quantization gemm inference-engine npu edge-ai hardware-accelerator gemv llm llm-inference llm-accelerator
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May 1, 2026 - SystemVerilog
Hardware Accelerator implementation for solving an ordinary differential equation using Runge Kutta Numerical methods using VHDL language
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Mar 9, 2024 - VHDL
Systolic-Tensor-Core, References the "Systolic Array" architecture used in TPUs.
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Mar 12, 2026 - C++
Hi everyone !! Here i have modified the vanila LeNet-5 model slightly and trained with the german traffic sign benchmark dataset. So by analysing the computation heavy layers i have designed an IP using Vitis HLS 2024.1 and implemented it in the PYNQ Z2 Platform.
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Dec 15, 2025 - C
This project implements AXI-based matrix multiply accelerator.
accelerator verilog systemverilog hardware-designs hardware-acceleration axi xsim vivado-simulator hardware-accelerator uvm-verification matrix-multiply-accumulate ai-accelerator
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Mar 7, 2026 - SystemVerilog
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