Sync from rust 2026/05/28

.github/workflows/stdarch.yml

@@ -21,7 +21,7 @@ jobs:
       fail-fast: false
       matrix:
         cargo_runner: [
-          "sde -future -rtm_mode full --",
+          "sde -cpuid-in /home/runner/work/rustc_codegen_gcc/rustc_codegen_gcc/tests/cpuid.def -rtm_mode full --",
           "",
         ]
 

example/mini_core.rs

@@ -577,12 +577,10 @@ fn eh_personality() -> ! {
     loop {}
 }
 
-#[lang = "drop_in_place"]
-#[allow(unconditional_recursion)]
-pub unsafe fn drop_in_place<T: ?Sized>(to_drop: *mut T) {
+#[lang = "drop_glue"]
+pub unsafe fn drop_glue<T: ?Sized>(_to_drop: &mut T) {
     // Code here does not matter - this is replaced by the
     // real drop glue by the compiler.
-    drop_in_place(to_drop);
 }
 
 #[lang = "unpin"]

libgccjit.version

@@ -1 +1 @@
-6f155cc3f5a2dff33afe6cc3ed6c2e0e605ae6a3
+d98bd412c7fb6bf8f2258e75f2e2b42f56a06bc1

rust-toolchain

@@ -1,3 +1,3 @@
 [toolchain]
-channel = "nightly-2026-05-06"
+channel = "nightly-2026-05-28"
 components = ["rust-src", "rustc-dev", "llvm-tools-preview"]

src/abi.rs

@@ -245,6 +245,8 @@ pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &Arch) -> Option<FnAttri
         // possible to declare an `extern "custom"` block, so the backend still needs a calling
         // convention for declaring foreign functions.
         CanonAbi::Custom => return None,
+        // gcc/gccjit does not have anything for Swift's calling convention.
+        CanonAbi::Swift => panic!("gcc/gccjit backend does not support Swift calling convention"),
         CanonAbi::Arm(arm_call) => match arm_call {
             ArmCall::CCmseNonSecureCall => FnAttribute::ArmCmseNonsecureCall,
             ArmCall::CCmseNonSecureEntry => FnAttribute::ArmCmseNonsecureEntry,

src/back/write.rs

@@ -29,16 +29,8 @@ pub(crate) fn codegen(
         let lto_mode = module.module_llvm.lto_mode;
         let lto_supported = module.module_llvm.lto_supported;
 
-        let bc_out = cgcx.output_filenames.temp_path_for_cgu(
-            OutputType::Bitcode,
-            &module.name,
-            cgcx.invocation_temp.as_deref(),
-        );
-        let obj_out = cgcx.output_filenames.temp_path_for_cgu(
-            OutputType::Object,
-            &module.name,
-            cgcx.invocation_temp.as_deref(),
-        );
+        let bc_out = cgcx.output_filenames.temp_path_for_cgu(OutputType::Bitcode, &module.name);
+        let obj_out = cgcx.output_filenames.temp_path_for_cgu(OutputType::Object, &module.name);
 
         if config.bitcode_needed() {
             let _timer =
@@ -79,22 +71,15 @@ pub(crate) fn codegen(
         }
 
         if config.emit_ir {
-            let out = cgcx.output_filenames.temp_path_for_cgu(
-                OutputType::LlvmAssembly,
-                &module.name,
-                cgcx.invocation_temp.as_deref(),
-            );
+            let out =
+                cgcx.output_filenames.temp_path_for_cgu(OutputType::LlvmAssembly, &module.name);
             std::fs::write(out, "").expect("write file");
         }
 
         if config.emit_asm {
             let _timer =
                 prof.generic_activity_with_arg("GCC_module_codegen_emit_asm", &*module.name);
-            let path = cgcx.output_filenames.temp_path_for_cgu(
-                OutputType::Assembly,
-                &module.name,
-                cgcx.invocation_temp.as_deref(),
-            );
+            let path = cgcx.output_filenames.temp_path_for_cgu(OutputType::Assembly, &module.name);
             context.compile_to_file(OutputKind::Assembler, path.to_str().expect("path to str"));
         }
 
@@ -212,7 +197,6 @@ pub(crate) fn codegen(
         config.emit_asm,
         config.emit_ir,
         &cgcx.output_filenames,
-        cgcx.invocation_temp.as_deref(),
     )
 }
 

src/builder.rs

@@ -418,8 +418,16 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
                 self.location,
                 self.cx.context.new_call_through_ptr(self.location, func_ptr, &args),
             );
-            // Return dummy value when not having return value.
-            self.context.new_rvalue_zero(self.isize_type)
+            // Return dummy value when not having return value, unless the intrinsic adapter
+            // needs to synthesize a non-void LLVM-level result from out-parameters.
+            llvm::adjust_intrinsic_return_value(
+                self,
+                self.context.new_rvalue_zero(self.isize_type),
+                &func_name,
+                &args,
+                args_adjusted,
+                orig_args,
+            )
         }
     }
 

src/context.rs

@@ -19,7 +19,7 @@ use rustc_middle::ty::{self, ExistentialTraitRef, Instance, Ty, TyCtxt};
 use rustc_session::Session;
 #[cfg(feature = "master")]
 use rustc_session::config::DebugInfo;
-use rustc_span::{DUMMY_SP, Span, respan};
+use rustc_span::{DUMMY_SP, Span, Symbol, respan};
 use rustc_target::spec::{HasTargetSpec, HasX86AbiOpt, Target, TlsModel, X86Abi};
 
 #[cfg(feature = "master")]
@@ -497,6 +497,10 @@ impl<'gcc, 'tcx> MiscCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
             None
         }
     }
+
+    fn intrinsic_call_expects_place_always(&self, _name: Symbol) -> bool {
+        true
+    }
 }
 
 impl<'gcc, 'tcx> HasTyCtxt<'tcx> for CodegenCx<'gcc, 'tcx> {

src/intrinsic/llvm.rs

@@ -478,6 +478,26 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
                 new_args.push(variable.get_address(None));
                 args = new_args.into();
             }
+            "__builtin_ia32_2intersectd128"
+            | "__builtin_ia32_2intersectq128"
+            | "__builtin_ia32_2intersectd256"
+            | "__builtin_ia32_2intersectq256"
+            | "__builtin_ia32_2intersectd512"
+            | "__builtin_ia32_2intersectq512" => {
+                let old_args = args.to_vec();
+                let mut new_args = vec![];
+                let arg1_type = gcc_func.get_param_type(0);
+                let first_mask =
+                    builder.current_func().new_local(None, arg1_type, "return_2intersect_arg1");
+                let arg2_type = gcc_func.get_param_type(1);
+                let second_mask =
+                    builder.current_func().new_local(None, arg2_type, "return_2intersect_arg2");
+                new_args.push(first_mask.get_address(None));
+                new_args.push(second_mask.get_address(None));
+                new_args.push(old_args[0]);
+                new_args.push(old_args[1]);
+                args = new_args.into();
+            }
             "__builtin_ia32_vpermt2varqi512_mask"
             | "__builtin_ia32_vpermt2varqi256_mask"
             | "__builtin_ia32_vpermt2varqi128_mask"
@@ -489,6 +509,23 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
                 let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1);
                 args = vec![new_args[1], new_args[0], new_args[2], minus_one].into();
             }
+            "__builtin_ia32_fpclassph128_mask"
+            | "__builtin_ia32_fpclassph256_mask"
+            | "__builtin_ia32_fpclassph512_mask"
+            | "__builtin_ia32_fpclasspd128_mask"
+            | "__builtin_ia32_fpclassps128_mask"
+            | "__builtin_ia32_fpclasspd256_mask"
+            | "__builtin_ia32_fpclassps256_mask"
+            | "__builtin_ia32_fpclasspd512_mask"
+            | "__builtin_ia32_fpclassps512_mask"
+            | "__builtin_ia32_vpshufbitqmb128_mask"
+            | "__builtin_ia32_vpshufbitqmb256_mask"
+            | "__builtin_ia32_vpshufbitqmb512_mask" => {
+                let new_args = args.to_vec();
+                let arg3_type = gcc_func.get_param_type(2);
+                let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1);
+                args = vec![new_args[0], new_args[1], minus_one].into();
+            }
             "__builtin_ia32_xrstor"
             | "__builtin_ia32_xrstor64"
             | "__builtin_ia32_xsavec"
@@ -854,6 +891,25 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(
                 &[random_number, success_variable.to_rvalue()],
             );
         }
+        "__builtin_ia32_2intersectd128"
+        | "__builtin_ia32_2intersectq128"
+        | "__builtin_ia32_2intersectd256"
+        | "__builtin_ia32_2intersectq256"
+        | "__builtin_ia32_2intersectd512"
+        | "__builtin_ia32_2intersectq512" => {
+            let first_mask = args[0].dereference(None).to_rvalue();
+            let second_mask = args[1].dereference(None).to_rvalue();
+            let field1 = builder.context.new_field(None, first_mask.get_type(), "first_mask");
+            let field2 = builder.context.new_field(None, second_mask.get_type(), "second_mask");
+            let struct_type =
+                builder.context.new_struct_type(None, "vp2intersect_result", &[field1, field2]);
+            return_value = builder.context.new_struct_constructor(
+                None,
+                struct_type.as_type(),
+                None,
+                &[first_mask, second_mask],
+            );
+        }
         "fma" => {
             let f16_type = builder.context.new_c_type(CType::Float16);
             return_value = builder.context.new_cast(None, return_value, f16_type);
@@ -1182,6 +1238,9 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.avx512.mask.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask",
         "llvm.x86.avx512.mask.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask",
         "llvm.x86.avx512.mask.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask",
+        "llvm.x86.avx512.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask",
+        "llvm.x86.avx512.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask",
+        "llvm.x86.avx512.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask",
         "llvm.x86.avx512.mask.ucmp.w.512" => "__builtin_ia32_ucmpw512_mask",
         "llvm.x86.avx512.mask.ucmp.w.256" => "__builtin_ia32_ucmpw256_mask",
         "llvm.x86.avx512.mask.ucmp.w.128" => "__builtin_ia32_ucmpw128_mask",
@@ -1339,11 +1398,20 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_v8bf",
         "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_v16bf",
         "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_v32bf",
+        "llvm.x86.vcvtneps2bf16128" => "__builtin_ia32_cvtneps2bf16_v4sf",
+        "llvm.x86.vcvtneps2bf16256" => "__builtin_ia32_cvtneps2bf16_v8sf",
+        "llvm.x86.avx512bf16.mask.cvtneps2bf16.128" => "__builtin_ia32_cvtneps2bf16_v4sf_mask",
         "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_v8sf",
         "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_v16sf",
         "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_v4sf",
         "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_v8sf",
         "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_v16sf",
+        "llvm.x86.avx512.vp2intersect.d.128" => "__builtin_ia32_2intersectd128",
+        "llvm.x86.avx512.vp2intersect.q.128" => "__builtin_ia32_2intersectq128",
+        "llvm.x86.avx512.vp2intersect.d.256" => "__builtin_ia32_2intersectd256",
+        "llvm.x86.avx512.vp2intersect.q.256" => "__builtin_ia32_2intersectq256",
+        "llvm.x86.avx512.vp2intersect.d.512" => "__builtin_ia32_2intersectd512",
+        "llvm.x86.avx512.vp2intersect.q.512" => "__builtin_ia32_2intersectq512",
         "llvm.x86.pclmulqdq.512" => "__builtin_ia32_vpclmulqdq_v8di",
         "llvm.x86.pclmulqdq.256" => "__builtin_ia32_vpclmulqdq_v4di",
         "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask",
@@ -1577,6 +1645,18 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.avx512.uitofp.round.v4f64.v4i64" => "__builtin_ia32_cvtuqq2pd256_mask",
         "llvm.x86.avx512.uitofp.round.v8f32.v8i64" => "__builtin_ia32_cvtuqq2ps512_mask",
         "llvm.x86.avx512.uitofp.round.v4f32.v4i64" => "__builtin_ia32_cvtuqq2ps256_mask",
+        "llvm.x86.avx512fp16.fpclass.ph.128" => "__builtin_ia32_fpclassph128_mask",
+        "llvm.x86.avx512fp16.mask.cmp.ph.128" => "__builtin_ia32_cmpph128_mask",
+        "llvm.x86.avx512fp16.fpclass.ph.256" => "__builtin_ia32_fpclassph256_mask",
+        "llvm.x86.avx512fp16.fpclass.ph.512" => "__builtin_ia32_fpclassph512_mask",
+        "llvm.x86.avx512fp16.mask.cmp.ph.256" => "__builtin_ia32_cmpph256_mask",
+        "llvm.x86.avx512fp16.mask.cmp.ph.512" => "__builtin_ia32_cmpph512_mask_round",
+        "llvm.x86.avx512.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask",
+        "llvm.x86.avx512.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask",
+        "llvm.x86.avx512.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask",
+        "llvm.x86.avx512.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask",
+        "llvm.x86.avx512.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask",
+        "llvm.x86.avx512.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask",
 
         // FIXME: support the tile builtins:
         "llvm.x86.ldtilecfg" => "__builtin_trap",
@@ -1607,6 +1687,10 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.tcvtrowd2psi" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phhi" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phli" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16h" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16hi" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16l" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16li" => "__builtin_trap",
         "llvm.x86.tcmmimfp16ps" => "__builtin_trap",
         "llvm.x86.tcmmrlfp16ps" => "__builtin_trap",