tech/mm/fastrpc: Add ADSP and CDSP support on Kaanapali SoC #520
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added 4 commits
January 14, 2026 11:31
Kaanapali introduces changes in DSP IOVA layout and CDSP DMA addressing that differ from previous SoCs. The SID field moves within the physical address, and CDSP now supports a wider DMA range, requiring updated sid_pos and DMA mask handling in the driver. Link: https://lore.kernel.org/all/20251226070534.602021-2-kumari.pallavi@oss.qualcomm.com/ Signed-off-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vkatoch@qti.qualcomm.com>
The fields buf->phys and map->phys currently store DMA addresses returned by dma_map_*() APIs, not physical addresses. This naming is misleading and may lead to incorrect assumptions about the address type and its translation. Rename these fields from phys to dma_addr to improve code clarity and align with kernel conventions for dma_addr_t usage. Link: https://lore.kernel.org/all/20251226070534.602021-3-kumari.pallavi@oss.qualcomm.com/ Signed-off-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vkatoch@qti.qualcomm.com>
Implement the new IOVA formatting required by the DSP architecture change on Kaanapali SoC. Place the SID for DSP DMA transactions at bit 56 in the physical address. This placement is necessary for the DSPs to correctly identify streams and operate as intended. To address this, set SID position to bit 56 via OF matching on the fastrpc node; otherwise, default to legacy 32-bit placement. This change ensures consistent SID placement across DSPs. Link: https://lore.kernel.org/all/20251226070534.602021-4-kumari.pallavi@oss.qualcomm.com/ Signed-off-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vkatoch@qti.qualcomm.com>
…i SoC DSP currently supports 32-bit IOVA (32-bit PA + 4-bit SID) for both Q6 and user DMA (uDMA) access. This is being upgraded to 34-bit PA + 4-bit SID due to a hardware revision in CDSP for Kaanapali SoC, which expands the DMA addressable range. Update DMA bits configuration in the driver to support CDSP on Kaanapali SoC. Set the default `dma_bits` to 32-bit and update it to 34-bit based on CDSP and OF matching on the fastrpc node. Link: https://lore.kernel.org/all/20251226070534.602021-5-kumari.pallavi@oss.qualcomm.com/ Signed-off-by: Kumari Pallavi <kumari.pallavi@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Vinayak Katoch <vkatoch@qti.qualcomm.com>
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This series adds support for updated DSP IOVA layout and CDSP DMA addressing on Kaanapali SoC.
Patch 1 adds dt-bindings compatible for Kaanapali to support changes in DSP IOVA layout and CDSP DMA addressing.
Patch 2 renames phys fields to dma_addr for clarity and alignment with kernel conventions.
Patch 3 implements the new DSP IOVA formatting by placing the SID at bit 56 in the physical address for Kaanapali SoC.
Patch 4 updates the DMA bits configuration to support CDSP's expanded DMA range (34-bit PA + 4-bit SID) on Kaanapali SoC.
Link: https://lore.kernel.org/all/20251226070534.602021-1-kumari.pallavi@oss.qualcomm.com/