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Add WaveActiveBitOr tests #973
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bfccb9a
add waveactivebitor tests
bob80905 db97e15
little bit of cleanup
bob80905 0a35d05
iteration
bob80905 5bc6c69
Merge branch 'main' into add_waveactivebitor_tests
bob80905 f7fc15f
address file renaming suggestion
bob80905 7edc5b5
Merge branch 'main' into add_waveactivebitor_tests
bob80905 62b5a28
rename to convergence
bob80905 25f2fa2
iterate
bob80905 e071203
address Justin
bob80905 55ab071
nit, self review
bob80905 04ff740
variable renaming
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,170 @@ | ||
| #--- source.hlsl | ||
| StructuredBuffer<uint> In : register(t0); | ||
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| RWStructuredBuffer<uint> Out1 : register(u1); // branch A | ||
| RWStructuredBuffer<uint> Out2 : register(u2); // branch B | ||
| RWStructuredBuffer<uint> Out3 : register(u3); // reconverged | ||
| RWStructuredBuffer<uint> Out4 : register(u4); // loop | ||
| RWStructuredBuffer<uint> Out5 : register(u5); // divergent loop | ||
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| [numthreads(4,1,1)] | ||
| void main(uint3 TID : SV_GroupThreadID) { | ||
| uint V = In[TID.x]; | ||
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| // divergent branch | ||
| if (TID.x < 2) | ||
| Out1[TID.x] = WaveActiveBitOr(V); | ||
| else | ||
| Out2[TID.x] = WaveActiveBitOr(V); | ||
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| // reconverged wave op | ||
| Out3[TID.x] = WaveActiveBitOr(V); | ||
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| // loop case | ||
| uint R = V; | ||
| for (uint i = 0; i < 2; i++) | ||
| R = WaveActiveBitOr(R); | ||
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| Out4[TID.x] = R; | ||
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| // divergent loop: each thread iterates TID.x times | ||
| // thread 0: 0 iters, thread 1: 1 iter, thread 2: 2 iters, thread 3: 3 iters | ||
| uint R2 = V; | ||
| for (uint j = 0; j < TID.x; j++) | ||
| R2 = WaveActiveBitOr(R2); | ||
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| Out5[TID.x] = R2; | ||
| } | ||
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| #--- pipeline.yaml | ||
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| --- | ||
| Shaders: | ||
| - Stage: Compute | ||
| Entry: main | ||
| DispatchSize: [1, 1, 1] | ||
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| Buffers: | ||
|
|
||
| - Name: In | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [ 0x11, 0x12, 0x14, 0x18 ] | ||
| - Name: Out1 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: Out2 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: Out3 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: Out4 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: Out5 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: ExpectedOut1 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x13, 0x13, 0x0, 0x0] | ||
| - Name: ExpectedOut2 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x0, 0x0, 0x1C, 0x1C] | ||
| - Name: ExpectedOut3 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x1F, 0x1F, 0x1F, 0x1F] | ||
| - Name: ExpectedOut4 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x1F, 0x1F, 0x1F, 0x1F] | ||
| - Name: ExpectedOut5 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x11, 0x1E, 0x1E, 0x1E] | ||
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| Results: | ||
| - Result: ExpectedOut1 | ||
| Rule: BufferExact | ||
| Actual: Out1 | ||
| Expected: ExpectedOut1 | ||
| - Result: ExpectedOut2 | ||
| Rule: BufferExact | ||
| Actual: Out2 | ||
| Expected: ExpectedOut2 | ||
| - Result: ExpectedOut3 | ||
| Rule: BufferExact | ||
| Actual: Out3 | ||
| Expected: ExpectedOut3 | ||
| - Result: ExpectedOut4 | ||
| Rule: BufferExact | ||
| Actual: Out4 | ||
| Expected: ExpectedOut4 | ||
| - Result: ExpectedOut5 | ||
| Rule: BufferExact | ||
| Actual: Out5 | ||
| Expected: ExpectedOut5 | ||
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|
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| DescriptorSets: | ||
| - Resources: | ||
| - Name: In | ||
| Kind: StructuredBuffer | ||
| DirectXBinding: | ||
| Register: 0 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 0 | ||
| - Name: Out1 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 1 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 1 | ||
| - Name: Out2 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 2 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 2 | ||
| - Name: Out3 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 3 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 3 | ||
| - Name: Out4 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 4 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 4 | ||
| - Name: Out5 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 5 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 5 | ||
| ... | ||
| #--- end | ||
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| # Bug: https://github.com/llvm/llvm-project/issues/188323 | ||
| # XFAIL: Vulkan && Clang | ||
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| # RUN: split-file %s %t | ||
| # RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl | ||
| # RUN: %offloader %t/pipeline.yaml %t.o |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,178 @@ | ||
| #--- source.hlsl | ||
| StructuredBuffer<uint4> In : register(t0); | ||
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| RWStructuredBuffer<uint> Out1 : register(u1); | ||
| RWStructuredBuffer<uint2> Out2 : register(u2); | ||
| RWStructuredBuffer<uint3> Out3 : register(u3); | ||
| RWStructuredBuffer<uint4> Out4 : register(u4); | ||
| RWStructuredBuffer<uint4> Out5 : register(u5); | ||
|
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||
|
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| [numthreads(4,1,1)] | ||
| void main(uint3 TID : SV_GroupThreadID) { | ||
| uint4 V = In[TID.x]; | ||
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| Out1[TID.x] = WaveActiveBitOr(V.x); | ||
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| Out2[TID.x] = WaveActiveBitOr(V.xy); | ||
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| uint3 R3 = WaveActiveBitOr(V.xyz); | ||
| Out3[TID.x].xyz = R3; | ||
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| Out4[TID.x] = WaveActiveBitOr(V); | ||
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| // constant folding uint4 | ||
| Out5[TID.x] = WaveActiveBitOr(uint4(1,2,3,4)); | ||
|
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| } | ||
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| #--- pipeline.yaml | ||
|
|
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| --- | ||
| Shaders: | ||
| - Stage: Compute | ||
| Entry: main | ||
| DispatchSize: [1, 1, 1] | ||
|
|
||
| Buffers: | ||
| - Name: In | ||
| Format: UInt32 | ||
| Stride: 16 | ||
| Data: [ | ||
| 0x11, 0x2, 0x4, 0x8, | ||
| 0x10, 0x20, 0x40, 0x80, | ||
| 0x100, 0x200, 0x400, 0x800, | ||
| 0x1000, 0x2000, 0x4000, 0x8000 | ||
| ] | ||
|
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||
| - Name: Out1 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| FillSize: 16 | ||
| - Name: Out2 | ||
| Format: UInt32 | ||
| Stride: 8 | ||
| FillSize: 32 | ||
| - Name: Out3 | ||
| Format: UInt32 | ||
| Stride: 12 | ||
| FillSize: 48 | ||
| - Name: Out4 | ||
| Format: UInt32 | ||
| Stride: 16 | ||
| FillSize: 64 | ||
| - Name: Out5 | ||
| Format: UInt32 | ||
| Stride: 16 | ||
| FillSize: 64 | ||
|
|
||
| - Name: ExpectedOut1 | ||
| Format: UInt32 | ||
| Stride: 4 | ||
| Data: [0x1111, 0x1111, 0x1111, 0x1111] | ||
| - Name: ExpectedOut2 | ||
| Format: UInt32 | ||
| Stride: 8 | ||
| Data: [ | ||
| 0x1111, 0x2222, | ||
| 0x1111, 0x2222, | ||
| 0x1111, 0x2222, | ||
| 0x1111, 0x2222 | ||
| ] | ||
| - Name: ExpectedOut3 | ||
| Format: UInt32 | ||
| Stride: 12 | ||
| Data: [ | ||
| 0x1111, 0x2222, 0x4444, | ||
| 0x1111, 0x2222, 0x4444, | ||
| 0x1111, 0x2222, 0x4444, | ||
| 0x1111, 0x2222, 0x4444 | ||
| ] | ||
| - Name: ExpectedOut4 | ||
| Format: UInt32 | ||
| Stride: 16 | ||
| Data: [ | ||
| 0x1111, 0x2222, 0x4444, 0x8888, | ||
| 0x1111, 0x2222, 0x4444, 0x8888, | ||
| 0x1111, 0x2222, 0x4444, 0x8888, | ||
| 0x1111, 0x2222, 0x4444, 0x8888 | ||
| ] | ||
| - Name: ExpectedOut5 | ||
| Format: UInt32 | ||
| Stride: 16 | ||
| Data: [ 0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4, | ||
| 0x1, 0x2, 0x3, 0x4, 0x1, 0x2, 0x3, 0x4 ] | ||
|
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||
|
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||
| Results: | ||
| - Result: ExpectedOut1 | ||
| Rule: BufferExact | ||
| Actual: Out1 | ||
| Expected: ExpectedOut1 | ||
| - Result: ExpectedOut2 | ||
| Rule: BufferExact | ||
| Actual: Out2 | ||
| Expected: ExpectedOut2 | ||
| - Result: ExpectedOut3 | ||
| Rule: BufferExact | ||
| Actual: Out3 | ||
| Expected: ExpectedOut3 | ||
| - Result: ExpectedOut4 | ||
| Rule: BufferExact | ||
| Actual: Out4 | ||
| Expected: ExpectedOut4 | ||
| - Result: ExpectedOut5 | ||
| Rule: BufferExact | ||
| Actual: Out5 | ||
| Expected: ExpectedOut5 | ||
|
|
||
| DescriptorSets: | ||
| - Resources: | ||
| - Name: In | ||
| Kind: StructuredBuffer | ||
| DirectXBinding: | ||
| Register: 0 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 0 | ||
| - Name: Out1 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 1 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 1 | ||
| - Name: Out2 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 2 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 2 | ||
| - Name: Out3 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 3 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 3 | ||
| - Name: Out4 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 4 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 4 | ||
| - Name: Out5 | ||
| Kind: RWStructuredBuffer | ||
| DirectXBinding: | ||
| Register: 5 | ||
| Space: 0 | ||
| VulkanBinding: | ||
| Binding: 5 | ||
| ... | ||
| #--- end | ||
|
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||
| # RUN: split-file %s %t | ||
| # RUN: %dxc_target -T cs_6_5 -fvk-use-dx-layout -Fo %t.o %t/source.hlsl | ||
| # RUN: %offloader %t/pipeline.yaml %t.o | ||
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Since we're using or here, I think specifying the inputs and outputs in hex will be clearer.