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[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well #172111

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Merged
mshockwave merged 1 commit into from
Dec 16, 2025
Merged

[RISCV] Guard zero-stride load SchedPredicate with subtarget feature as well #172111

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7 changes: 6 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrPredicates.td
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Expand Up @@ -12,7 +12,12 @@

// This predicate is true when the rs2 operand of vlse or vsse is x0, false
// otherwise.
def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
// Note: in our pseudo RVV MachinInstr, rs2 is the fourth operand. However,
// it's the third operand of its MCInst form, so this predicate will not
// be triggered by llvm-mca, which checks against MCInst.
def VLDSX0Pred
: AllOfSchedPreds<[FeatureSchedPredicate<TuneOptimizedZeroStrideLoad>,
MCSchedPredicate<CheckRegOperand<3, X0>>]>;

// This scheduling predicate is true when subtarget feature TuneHasSingleElementVecFP64
// is enabled.
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