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Feature/rv64 rvv support #508

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edffa04
RISC-V64 arch. port support RVV Extension;
goodnorning Mar 4, 2026
3fe3f04
RISC-V64 qemu_virt example support RVV Extension;
goodnorning Mar 4, 2026
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1 change: 1 addition & 0 deletions ports/risc-v64/gnu/example_build/qemu_virt/csr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#define MSTATUS_MIE (1L << 3) // machine-mode interrupt enable.
#define MSTATUS_MPIE (1L << 7)
#define MSTATUS_FS (1L << 13)
#define MSTATUS_VS (1L << 9)

// Machine-mode Interrupt Enable
#define MIE_MTIE (1L << 7)
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5 changes: 5 additions & 0 deletions ports/risc-v64/gnu/example_build/qemu_virt/demo_threadx.c
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Expand Up @@ -4,8 +4,13 @@

#include "tx_api.h"
#include "uart.h"
#if defined(__riscv_vector)
#define DEMO_STACK_SIZE (1024 + 16448) /* 16448 for RVV Extension */
#define DEMO_BYTE_POOL_SIZE (9180 + 148032) /* 148032 for RVV Extension */
#else
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9180
#endif
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100

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2 changes: 1 addition & 1 deletion ports/risc-v64/gnu/example_build/qemu_virt/entry.s
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Expand Up @@ -41,7 +41,7 @@ _start:
li x30, 0
li x31, 0
la t0, _sysstack_start
li t1, 0x1000
li t1, 0x5000
add sp, t0, t1
la t0, _bss_start
la t1, _bss_end
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2 changes: 1 addition & 1 deletion ports/risc-v64/gnu/example_build/qemu_virt/link.lds
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Expand Up @@ -41,7 +41,7 @@ SECTIONS
.stack : {
. = ALIGN(4096);
_sysstack_start = .;
. += 0x1000;
. += 0x5000;
_sysstack_end = .;
}

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11 changes: 11 additions & 0 deletions ports/risc-v64/gnu/example_build/qemu_virt/tx_initialize_low_level.S
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Expand Up @@ -70,6 +70,13 @@
#else
addi sp, sp, -256 // Allocate space for all registers - without floating point enabled (32*8)
#endif
#if defined(__riscv_vector)
/* Allocate space for vector registers */
csrr t4, vlenb
slli t4, t4, 5
addi t4, t4, 5*8
sub sp, sp, t4
#endif

sd x1, 224(sp) // Store RA (28*8 = 224, because call will override ra [ra is a callee register in riscv])

Expand Down Expand Up @@ -153,6 +160,10 @@ _tx_initialize_low_level:
li t0, MSTATUS_FS
csrrs zero, mstatus, t0 // set MSTATUS_FS bit to open f/d isa in riscv
fscsr x0
#endif
#ifdef __riscv_vector
li t0, MSTATUS_VS
csrrs zero, mstatus, t0 // set MSTATUS_VS bit to open vector isa in riscv
#endif
addi sp, sp, -8
sd ra, 0(sp)
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12 changes: 10 additions & 2 deletions ports/risc-v64/gnu/inc/tx_port.h
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Expand Up @@ -105,15 +105,23 @@ typedef unsigned short USHORT;
thread creation is less than this value, the thread create call will return an error. */

#ifndef TX_MINIMUM_STACK
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
#if defined(__riscv_vector)
#define TX_MINIMUM_STACK (1024 + 16448) /* Minimum stack size for this port */
#else
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
#endif
#endif


/* Define the system timer thread's default stack size and priority. These are only applicable
if TX_TIMER_PROCESS_IN_ISR is not defined. */

#ifndef TX_TIMER_THREAD_STACK_SIZE
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#if defined(__riscv_vector)
#define TX_TIMER_THREAD_STACK_SIZE (1024 + 16448) /* Default timer thread stack size */
#else
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#endif

#ifndef TX_TIMER_THREAD_PRIORITY
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130 changes: 130 additions & 0 deletions ports/risc-v64/gnu/src/tx_thread_context_restore.S
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Expand Up @@ -138,6 +138,36 @@ _tx_thread_context_restore:
csrw fcsr, t0
#endif

#if defined(__riscv_vector)
/* Recover vector registers v0-v31 */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t1, sp, 64*8
#else
addi t1, sp, 31*8
#endif
addi t2, t1, 5*8
vsetvli t3, zero, e8, m8, ta, ma
vle8.v v0, (t2) // Recover v0 ~ v7
add t2, t2, t3
vle8.v v8, (t2) // Recover v8 ~ v15
add t2, t2, t3
vle8.v v16, (t2) // Recover v16 ~ v23
add t2, t2, t3
vle8.v v24, (t2) // Recover v24 ~ v31
add t2, t2, t3

/* Recover vector CSRs */
ld t2, 0*8(t1)
ld t3, 1*8(t1)
ld t4, 2*8(t1)
vsetvl zero, t2, t3
csrw vstart, t4
ld t4, 3*8(t1)
csrw vxsat, t4
ld t4, 4*8(t1)
csrw vxrm, t4
#endif

/* Recover standard registers. */

/* Restore registers,
Expand Down Expand Up @@ -168,6 +198,10 @@ _tx_thread_context_restore:
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
or t1, t1, t0
#endif
#if defined(__riscv_vector)
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely

Expand All @@ -194,6 +228,21 @@ _tx_thread_context_restore:
#else
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
#endif

#if defined(__riscv_vector)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t0, sp, -65*8
#else
addi t0, sp, -32*8
#endif
csrr t1, vlenb // Get vector register byte length
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
add sp, sp, t1 // Recover vector stack frame

ld t1, 18*8(t0) // Recover t1
ld t0, 19*8(t0) // Recover t0
#endif
mret // Return to point of interrupt

/* } */
Expand Down Expand Up @@ -273,6 +322,36 @@ _tx_thread_no_preempt_restore:
csrw fcsr, t0 // Restore fcsr
#endif

#if defined(__riscv_vector)
/* Recover vector registers v0-v31 */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t1, sp, 64*8
#else
addi t1, sp, 31*8
#endif
addi t2, t1, 5*8
vsetvli t3, zero, e8, m8, ta, ma
vle8.v v0, (t2) // Recover v0 ~ v7
add t2, t2, t3
vle8.v v8, (t2) // Recover v8 ~ v15
add t2, t2, t3
vle8.v v16, (t2) // Recover v16 ~ v23
add t2, t2, t3
vle8.v v24, (t2) // Recover v24 ~ v31
add t2, t2, t3

/* Recover vector CSRs */
ld t2, 0*8(t1)
ld t3, 1*8(t1)
ld t4, 2*8(t1)
vsetvl zero, t2, t3
csrw vstart, t4
ld t4, 3*8(t1)
csrw vxsat, t4
ld t4, 4*8(t1)
csrw vxrm, t4
#endif

/* Recover the saved context and return to the point of interrupt. */

/* Recover standard registers. */
Expand All @@ -294,6 +373,10 @@ _tx_thread_no_preempt_restore:
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 // Set FS bits for FP state
or t1, t1, t0
#endif
#if defined(__riscv_vector)
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
or t1, t1, t0
#endif
csrw mstatus, t1 // Update mstatus safely

Expand All @@ -320,6 +403,21 @@ _tx_thread_no_preempt_restore:
#else
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
#endif

#if defined(__riscv_vector)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t0, sp, -65*8
#else
addi t0, sp, -32*8
#endif
csrr t1, vlenb // Get vector register byte length
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
add sp, sp, t1 // Recover vector stack frame

ld t1, 18*8(t0) // Recover t1
ld t0, 19*8(t0) // Recover t0
#endif
mret // Return to point of interrupt

/* }
Expand Down Expand Up @@ -362,6 +460,38 @@ _tx_thread_preempt_restore:
fsd f27, 58*8(t0) // Store fs11
#endif

#if defined(__riscv_vector)
/* Store vector registers and CSRs */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t1, t0, 64*8
#else
addi t1, t0, 31*8
#endif
/* Store vector CSRs */
csrr t2, vl // Store vl
sd t2, 0*8(t1)
csrr t2, vtype // Store vtype
sd t2, 1*8(t1)
csrr t2, vstart // Store vstart
sd t2, 2*8(t1)
csrr t2, vxrm // Store vxrm
sd t2, 3*8(t1)
csrr t2, vxsat // Store vxsat
sd t2, 4*8(t1)

/* Store vector registers v0-v31 */
addi t2, t1, 5*8
vsetvli t3, zero, e8, m8, ta, ma
vse8.v v0, 0(t2) // Store v0 ~ v7
add t2, t2, t3
vse8.v v8, 0(t2) // Store v8 ~ v15
add t2, t2, t3
vse8.v v16, 0(t2) // Store v16 ~ v23
add t2, t2, t3
vse8.v v24, 0(t2) // Store v24 ~ v31
add t2, t2, t3
#endif

/* Store standard preserved registers. */

sd x9, 11*8(t0) // Store s1
Expand Down
79 changes: 79 additions & 0 deletions ports/risc-v64/gnu/src/tx_thread_context_save.S
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Expand Up @@ -151,6 +151,38 @@ _tx_thread_context_save:
sd t0, 63*8(sp) // Store fcsr
#endif

#if defined(__riscv_vector)
/* Store vector registers and CSRs */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t1, sp, 64*8
#else
addi t1, sp, 31*8
#endif
/* Store vector CSRs */
csrr t2, vl // Store vl
sd t2, 0*8(t1)
csrr t2, vtype // Store vtype
sd t2, 1*8(t1)
csrr t2, vstart // Store vstart
sd t2, 2*8(t1)
csrr t2, vxrm // Store vxrm
sd t2, 3*8(t1)
csrr t2, vxsat // Store vxsat
sd t2, 4*8(t1)

/* Store vector registers v0-v31 */
addi t2, t1, 5*8
vsetvli t3, zero, e8, m8, ta, ma
vse8.v v0, 0(t2) // Store v0 ~ v7
add t2, t2, t3
vse8.v v8, 0(t2) // Store v8 ~ v15
add t2, t2, t3
vse8.v v16, 0(t2) // Store v16 ~ v23
add t2, t2, t3
vse8.v v24, 0(t2) // Store v24 ~ v31
add t2, t2, t3
#endif

#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
Expand Down Expand Up @@ -241,6 +273,38 @@ _tx_thread_not_nested_save:
sd t0, 63*8(sp) // Store fcsr
#endif

#if defined(__riscv_vector)
/* Store vector registers and CSRs */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t1, sp, 64*8
#else
addi t1, sp, 31*8
#endif
/* Store vector CSRs */
csrr t2, vl // Store vl
sd t2, 0*8(t1)
csrr t2, vtype // Store vtype
sd t2, 1*8(t1)
csrr t2, vstart // Store vstart
sd t2, 2*8(t1)
csrr t2, vxrm // Store vxrm
sd t2, 3*8(t1)
csrr t2, vxsat // Store vxsat
sd t2, 4*8(t1)

/* Store vector registers v0-v31 */
addi t2, t1, 5*8
vsetvli t3, zero, e8, m8, ta, ma
vse8.v v0, 0(t2) // Store v0 ~ v7
add t2, t2, t3
vse8.v v8, 0(t2) // Store v8 ~ v15
add t2, t2, t3
vse8.v v16, 0(t2) // Store v16 ~ v23
add t2, t2, t3
vse8.v v24, 0(t2) // Store v24 ~ v31
add t2, t2, t3
#endif

/* Save the current stack pointer in the thread's control block. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */

Expand Down Expand Up @@ -280,4 +344,19 @@ _tx_thread_idle_system_save:
#else
addi sp, sp, 32*8 // Recover the reserved stack space
#endif

#if defined(__riscv_vector)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t0, sp, -65*8
#else
addi t0, sp, -32*8
#endif
csrr t1, vlenb // Get vector register byte length
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
add sp, sp, t1 // Recover vector stack frame

ld t1, 18*8(t0) // Recover t1
ld t0, 19*8(t0) // Recover t0
#endif
ret // Return to calling ISR
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