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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

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13 changes: 12 additions & 1 deletion drivers/sim.c
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Original file line number Diff line number Diff line change
Expand Up @@ -955,7 +955,18 @@ static int step_0xxx_addr(struct sim_device *dev, uint16_t ins)
switch (info->src_amode) {

case MSP430_AMODE_REGISTER:
src_data = dev->regs[src];
if((ins&0xffc0)==0x03c0)
{
switch(ins&0x0030)
{
case 0x00:src_data=0;break;
case 0x10:src_data=0;break;
case 0x20:src_data=2;break;
case 0x30:src_data=2;break;
}
}
else
src_data = dev->regs[src];
break;

case MSP430_AMODE_IMMEDIATE:
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