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Verilog: comments and redundant synth_expr call#1672

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kroening merged 1 commit intomainfrom
synthesis-comments
Feb 25, 2026
Merged

Verilog: comments and redundant synth_expr call#1672
kroening merged 1 commit intomainfrom
synthesis-comments

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This adds comments to the arguments of assignment_rec, which indicate that a redundant call to synth_expr can be removed.

This adds comments to the arguments of assignment_rec, which indicate that a
redundant call to synth_expr can be removed.
@kroening kroening marked this pull request as ready for review February 25, 2026 00:50
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@tautschnig tautschnig left a comment

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Wouldn't it be better to introduce synth_exprt and synth_lhs_exprt (both deriving from exprt) to replace good intentions by a compiler-provided mechanism?

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Wouldn't it be better to introduce synth_exprt and synth_lhs_exprt (both deriving from exprt) to replace good intentions by a compiler-provided mechanism?

You'd need predicates on types (you'd want a synthesised symbol_exprt, synthesised index expression etc).

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You'd need predicates on types (you'd want a synthesised symbol_exprt, synthesised index expression etc).

You could still wrap a symbol expression/index expression/etc. in that predicate? Just like the approach you introduced in the expression simplifier (to track changed/unchanged)?

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Approving so as not the block all the work building on top of this, but I'd still prefer a solution not based on comments.

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Approving so as not the block all the work building on top of this, but I'd still prefer a solution not based on comments.

Agreed; the synthesis part should likely get a redesign.

@kroening kroening merged commit e9c9f27 into main Feb 25, 2026
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@kroening kroening deleted the synthesis-comments branch February 25, 2026 19:42
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