Verilog: avoid full identifiers in parse tree #1522
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Parsing is too earny a stage to use full identifiers -- this replaces the use of full identifiers in the Verilog parse tree by the combination of scope prefix and base name.
tautschnig
approved these changes
Dec 27, 2025
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Parsing is too earny a stage to use full identifiers -- this replaces the use of full identifiers in the Verilog parse tree by the combination of scope prefix and base name.