arch/risc-v/k210: Add Watchdog Timer (WDT) driver support.

Documentation/platforms/risc-v/k210/index.rst

@@ -22,6 +22,20 @@ The driver supports querying clock frequencies for:
 CPU frequency can be configured at build time using the ``K210_CPU_FREQ``
 Kconfig option (default: 400 MHz, range: 40-600 MHz).
 
+Watchdog Timers
+===============
+
+The K210 has two independent watchdog timers (WDT0 and WDT1) for system
+reliability. Both are accessible as character drivers via the standard
+NuttX watchdog interface.
+
+* **WDT0**: Base address ``0x50400000``, IRQ 21
+* **WDT1**: Base address ``0x50410000``, IRQ 22
+* **Timeout range**: Programmable based on 16-bit counter
+
+Enable via Kconfig: ``CONFIG_K210_WDT`` (automatically selects
+``CONFIG_WATCHDOG``). Devices are ``/dev/watchdog0`` and ``/dev/watchdog1``.
+
 Supported Boards
 ================
 

arch/risc-v/include/k210/irq.h

@@ -36,6 +36,8 @@
 #ifdef CONFIG_K210_WITH_QEMU
 #define K210_IRQ_UART0    (RISCV_IRQ_MEXT + 4)
 #else
+#define K210_IRQ_WDT0     (RISCV_IRQ_MEXT + 21)
+#define K210_IRQ_WDT1     (RISCV_IRQ_MEXT + 22)
 #define K210_IRQ_UART0    (RISCV_IRQ_MEXT + 33)
 #endif
 

arch/risc-v/src/k210/CMakeLists.txt

@@ -32,4 +32,8 @@ if(CONFIG_BUILD_PROTECTED)
   list(APPEND SRCS k210_userspace.c)
 endif()
 
+if(CONFIG_K210_WDT)
+  list(APPEND SRCS k210_wdt.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/risc-v/src/k210/Kconfig

@@ -25,6 +25,20 @@ config K210_UART0
 	select ARCH_HAVE_SERIAL_TERMIOS
 	select K210_UART
 
+config K210_WDT
+	bool
+	select WATCHDOG
+
+config K210_WDT0
+	bool "WDT0"
+	default n
+	select K210_WDT
+
+config K210_WDT1
+	bool "WDT1"
+	default n
+	select K210_WDT
+
 endmenu
 
 config K210_CPU_FREQ

arch/risc-v/src/k210/Make.defs

@@ -35,3 +35,7 @@ CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c k210_sysctl.c
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += k210_userspace.c
 endif
+
+ifeq ($(CONFIG_K210_WDT),y)
+CHIP_CSRCS += k210_wdt.c
+endif

arch/risc-v/src/k210/hardware/k210_memorymap.h

@@ -40,6 +40,9 @@
 #define K210_GPIOHS_BASE  0x38001000
 #define K210_FPIOA_BASE   0x502B0000
 
+#define K210_WDT0_BASE    0x50400000
+#define K210_WDT1_BASE    0x50410000
+
 #define K210_SYSCTL_BASE  0x50440000
 
 #endif /* __ARCH_RISCV_SRC_K210_HARDWARE_K210_MEMORYMAP_H */

arch/risc-v/src/k210/hardware/k210_wdt.h

@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/risc-v/src/k210/hardware/k210_wdt.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_K210_HARDWARE_K210_WDT_H
+#define __ARCH_RISCV_SRC_K210_HARDWARE_K210_WDT_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define K210_WDT_CR_OFFSET          0x0000
+#define K210_WDT_TORR_OFFSET        0x0004
+#define K210_WDT_CCVR_OFFSET        0x0008
+#define K210_WDT_CRR_OFFSET         0x000c
+#define K210_WDT_STAT_OFFSET        0x0010
+#define K210_WDT_EOI_OFFSET         0x0014
+#define K210_WDT_PROT_LEVEL_OFFSET  0x001c
+
+#define K210_WDT_CR(base)           ((base) + K210_WDT_CR_OFFSET)
+#define K210_WDT_TORR(base)         ((base) + K210_WDT_TORR_OFFSET)
+#define K210_WDT_CCVR(base)         ((base) + K210_WDT_CCVR_OFFSET)
+#define K210_WDT_CRR(base)          ((base) + K210_WDT_CRR_OFFSET)
+#define K210_WDT_STAT(base)         ((base) + K210_WDT_STAT_OFFSET)
+#define K210_WDT_EOI(base)          ((base) + K210_WDT_EOI_OFFSET)
+
+#define K210_WDT_CR_ENABLE          0x00000001u
+#define K210_WDT_CR_RMOD_MASK       0x00000002u
+#define K210_WDT_CR_RMOD_RESET      0x00000000u
+#define K210_WDT_CR_RMOD_INTERRUPT  0x00000002u
+
+#define K210_WDT_TORR_TOP(n)        (((n) << 4) | ((n) << 0))
+
+#define K210_WDT_CRR_RESTART        0x00000076u
+
+#endif /* __ARCH_RISCV_SRC_K210_HARDWARE_K210_WDT_H */