add support for AD3532R/AD3532 DAC#3177
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kseerp wants to merge 3 commits intoanalogdevicesinc:mirror_ci/jic23/iio/testingfrom
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add support for AD3532R/AD3532 DAC#3177kseerp wants to merge 3 commits intoanalogdevicesinc:mirror_ci/jic23/iio/testingfrom
kseerp wants to merge 3 commits intoanalogdevicesinc:mirror_ci/jic23/iio/testingfrom
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Same as #3191, if you are upstreaming, please target branches in sync with upstream cycle (the mirror_ci branches), this helps to avoid using deprecated methods. |
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Please, don't include the CI/CD commit on your pr. |
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Add a new powerdown mode for DACs with 10kohm resistor to GND. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The AD3532R/AD3532 is a 16-channel version of the AD3530R/AD3530. This adds compatible strings for the AD3532R/AD3532. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The AD3532R/AD3532 is a 16-channel, 16-bit voltage output DAC. These devices use a dual-bank register architecture with base addresses at 0x1000 (bank 0) and 0x3000 (bank 1). Channels 0-7 are mapped to bank 0, while channels 8-15 are mapped to bank 1. To support the dual-bank architecture, a new ad3532r_set_dac_powerdown() function handles the 4-register powerdown mapping, where channels 0-7 use registers 0x1020/0x1021 and channels 8-15 use 0x3020/0x3021. The AD3532 variants also implement different powerdown modes (1kΩ, 10kΩ, three-state) compared to the AD3530/31 devices (1kΩ, 7.7kΩ, 32kΩ). The ad3530r_normal_op_mode() and ad3530r_setup() functions have been extended to configure dual-bank registers for reference control and output settings. New helper functions ad3532r_input_ch_reg() and ad3532r_trigger_sw_ldac_reg() provide bank-aware register addressing based on the channel number. Dynamic channel allocation is now used with chip-specific ext_info assignment to handle the different powerdown mode enums per variant. Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
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Hi, just to follow-up on this PR, let me know if changes are needed, or if it looks ok to proceed with upstream submission. Thanks |
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PR Description
These parts are unreleased but have BU approval to upstream the driver so it can be ready prior to RTS.
The AD3532R/AD3532 is a 16-channel, 16-bit voltage output DAC. These
devices use a dual-bank register architecture with base addresses at
0x1000 (bank 0) and 0x3000 (bank 1). Channels 0-7 are mapped to bank 0,
while channels 8-15 are mapped to bank 1.
Key Changes:
ad3532r_set_dac_powerdown()to handle 4-register powerdownmapping (
0x1020/0x1021for channels 0-7,0x3020/0x3021for 8-15)(differs from AD3530/31's 1kΩ, 7.7kΩ, 32kΩ modes)
ad3530r_normal_op_mode()andad3530r_setup()to configuredual-bank registers for reference control and output settings
ad3532r_input_ch_reg()andad3532r_trigger_sw_ldac_reg()forbank-aware register addressing
handle different powerdown mode enums per variant.
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PR Checklist