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Merge to tag jdk-21.0.12+4 #2259

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2ad08bb
8363943: ARM32: Represent Registers as values
May 21, 2026
f4d3e77
8384495: Update Libpng to 1.6.58
GoeLin May 21, 2026
51118e0
8380316: Test runtime/os/AvailableProcessors.java fails Invalid argument
May 22, 2026
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32 changes: 16 additions & 16 deletions src/hotspot/cpu/arm/arm_32.ad
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Expand Up @@ -62,22 +62,22 @@ register %{
// Integer/Long Registers
// ----------------------------

reg_def R_R0 (SOC, SOC, Op_RegI, 0, R(0)->as_VMReg());
reg_def R_R1 (SOC, SOC, Op_RegI, 1, R(1)->as_VMReg());
reg_def R_R2 (SOC, SOC, Op_RegI, 2, R(2)->as_VMReg());
reg_def R_R3 (SOC, SOC, Op_RegI, 3, R(3)->as_VMReg());
reg_def R_R4 (SOC, SOE, Op_RegI, 4, R(4)->as_VMReg());
reg_def R_R5 (SOC, SOE, Op_RegI, 5, R(5)->as_VMReg());
reg_def R_R6 (SOC, SOE, Op_RegI, 6, R(6)->as_VMReg());
reg_def R_R7 (SOC, SOE, Op_RegI, 7, R(7)->as_VMReg());
reg_def R_R8 (SOC, SOE, Op_RegI, 8, R(8)->as_VMReg());
reg_def R_R9 (SOC, SOE, Op_RegI, 9, R(9)->as_VMReg());
reg_def R_R10(NS, SOE, Op_RegI, 10, R(10)->as_VMReg());
reg_def R_R11(NS, SOE, Op_RegI, 11, R(11)->as_VMReg());
reg_def R_R12(SOC, SOC, Op_RegI, 12, R(12)->as_VMReg());
reg_def R_R13(NS, NS, Op_RegI, 13, R(13)->as_VMReg());
reg_def R_R14(SOC, SOC, Op_RegI, 14, R(14)->as_VMReg());
reg_def R_R15(NS, NS, Op_RegI, 15, R(15)->as_VMReg());
reg_def R_R0 (SOC, SOC, Op_RegI, 0, as_Register(0)->as_VMReg());
reg_def R_R1 (SOC, SOC, Op_RegI, 1, as_Register(1)->as_VMReg());
reg_def R_R2 (SOC, SOC, Op_RegI, 2, as_Register(2)->as_VMReg());
reg_def R_R3 (SOC, SOC, Op_RegI, 3, as_Register(3)->as_VMReg());
reg_def R_R4 (SOC, SOE, Op_RegI, 4, as_Register(4)->as_VMReg());
reg_def R_R5 (SOC, SOE, Op_RegI, 5, as_Register(5)->as_VMReg());
reg_def R_R6 (SOC, SOE, Op_RegI, 6, as_Register(6)->as_VMReg());
reg_def R_R7 (SOC, SOE, Op_RegI, 7, as_Register(7)->as_VMReg());
reg_def R_R8 (SOC, SOE, Op_RegI, 8, as_Register(8)->as_VMReg());
reg_def R_R9 (SOC, SOE, Op_RegI, 9, as_Register(9)->as_VMReg());
reg_def R_R10(NS, SOE, Op_RegI, 10, as_Register(10)->as_VMReg());
reg_def R_R11(NS, SOE, Op_RegI, 11, as_Register(11)->as_VMReg());
reg_def R_R12(SOC, SOC, Op_RegI, 12, as_Register(12)->as_VMReg());
reg_def R_R13(NS, NS, Op_RegI, 13, as_Register(13)->as_VMReg());
reg_def R_R14(SOC, SOC, Op_RegI, 14, as_Register(14)->as_VMReg());
reg_def R_R15(NS, NS, Op_RegI, 15, as_Register(15)->as_VMReg());

// ----------------------------
// Float/Double Registers
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/arm/assembler_arm_32.hpp
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Expand Up @@ -114,7 +114,7 @@ class RegisterSet {
}

RegisterSet(Register first, Register last) {
assert(first < last, "encoding constraint");
assert(first->encoding() < last->encoding(), "encoding constraint");
_encoding = (1 << (last->encoding() + 1)) - (1 << first->encoding());
}

Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/arm/c1_CodeStubs_arm.cpp
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Expand Up @@ -182,7 +182,7 @@ void MonitorEnterStub::emit_code(LIR_Assembler* ce) {
const Register lock_reg = _lock_reg->as_pointer_register();

ce->verify_reserved_argument_area_size(2);
if (obj_reg < lock_reg) {
if (obj_reg->encoding() < lock_reg->encoding()) {
__ stmia(SP, RegisterSet(obj_reg) | RegisterSet(lock_reg));
} else {
__ str(obj_reg, Address(SP));
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
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Expand Up @@ -2659,11 +2659,11 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,
const Register src_hi = src->as_register_hi();
assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");

if (src_lo < src_hi) {
if (src_lo->encoding() < src_hi->encoding()) {
null_check_offset = __ offset();
__ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
} else {
assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
assert(src_lo->encoding() < Rtemp->encoding(), "Rtemp is higher than any allocatable register");
__ mov(Rtemp, src_hi);
null_check_offset = __ offset();
__ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
Expand All @@ -2676,10 +2676,10 @@ void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type,
assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");

null_check_offset = __ offset();
if (dest_lo < dest_hi) {
if (dest_lo->encoding() < dest_hi->encoding()) {
__ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
} else {
assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
assert(dest_lo->encoding() < Rtemp->encoding(), "Rtemp is higher than any allocatable register");
__ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
__ mov(dest_hi, Rtemp);
}
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/arm/interp_masm_arm.cpp
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Expand Up @@ -406,7 +406,7 @@ void InterpreterMacroAssembler::pop_i(Register r) {

void InterpreterMacroAssembler::pop_l(Register lo, Register hi) {
assert_different_registers(lo, hi);
assert(lo < hi, "lo must be < hi");
assert(lo->encoding() < hi->encoding(), "lo must be < hi");
pop(RegisterSet(lo) | RegisterSet(hi));
}

Expand Down Expand Up @@ -456,7 +456,7 @@ void InterpreterMacroAssembler::push_i(Register r) {

void InterpreterMacroAssembler::push_l(Register lo, Register hi) {
assert_different_registers(lo, hi);
assert(lo < hi, "lo must be < hi");
assert(lo->encoding() < hi->encoding(), "lo must be < hi");
push(RegisterSet(lo) | RegisterSet(hi));
}

Expand Down
30 changes: 19 additions & 11 deletions src/hotspot/cpu/arm/register_arm.cpp
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Expand Up @@ -26,12 +26,19 @@
#include "register_arm.hpp"
#include "utilities/debug.hpp"

const int ConcreteRegisterImpl::max_gpr = ConcreteRegisterImpl::num_gpr;
const int ConcreteRegisterImpl::max_fpr = ConcreteRegisterImpl::num_fpr +
ConcreteRegisterImpl::max_gpr;
Register::RegisterImpl all_RegisterImpls [Register::number_of_registers + 1];
FloatRegister::FloatRegisterImpl all_FloatRegisterImpls [FloatRegister::number_of_registers + 1];
VFPSystemRegister::VFPSystemRegisterImpl all_VFPSystemRegisterImpls [VFPSystemRegister::number_of_registers + 1] {
{ -1 }, //vfpsnoreg
{ VFPSystemRegister::FPSID },
{ VFPSystemRegister::FPSCR },
{ VFPSystemRegister::MVFR0 },
{ VFPSystemRegister::MVFR1 }
};

const char* RegisterImpl::name() const {
const char* names[number_of_registers] = {
const char* Register::RegisterImpl::name() const {
static const char* names[number_of_registers + 1] = {
"noreg",
"r0", "r1", "r2", "r3", "r4", "r5", "r6",
#if (FP_REG_NUM == 7)
"fp",
Expand All @@ -46,13 +53,14 @@ const char* RegisterImpl::name() const {
#endif
"r12", "sp", "lr", "pc"
};
return is_valid() ? names[encoding()] : "noreg";
return names[encoding() + 1];
}

const char* FloatRegisterImpl::name() const {
const char* names[number_of_registers] = {
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
const char* FloatRegister::FloatRegisterImpl::name() const {
static const char* names[number_of_registers + 1] = {
"fnoreg",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31"
#ifdef COMPILER2
Expand All @@ -62,5 +70,5 @@ const char* FloatRegisterImpl::name() const {
"s56", "s57?","s58", "s59?","s60", "s61?","s62", "s63?"
#endif
};
return is_valid() ? names[encoding()] : "fnoreg";
return names[encoding() + 1];
}
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