x86: implement AVX2 kernel for ggml_vec_dot_q1_0_g128_q8_0

[SimesD61]

Problem

The x86 implementation of ggml_vec_dot_q1_0_g128_q8_0 in ggml/src/ggml-cpu/arch/x86/quants.c was a stub that immediately fell through to the scalar generic fallback:

void ggml_vec_dot_q1_0_g128_q8_0(...) {
    ggml_vec_dot_q1_0_g128_q8_0_generic(...);
}

The ARM NEON implementation was already fully vectorized. On x86 this meant Bonsai 8B ran at ~0.04 tok/s — 67× slower than the ARM CPU path.

Solution

Full AVX2 implementation using the same algorithm as the NEON kernel:

• vpshufb bit expansion: Each 32-bit sub-block is broadcast to 32 bytes via _mm_shuffle_epi8, then AND+cmpeq decodes 1-bit weights to sign bytes (+1/-1)
• INT8 dot product: maddubs_epi16 + madd_epi16 for efficient 8-bit multiply-accumulate
• 4 independent FMA accumulators: Hides the 5-cycle FMA latency on Skylake (matches one accumulator per sub-block of the block_q1_0_g128 layout)
• Falls back to generic on non-AVX2 targets

Performance (Intel i7-8700B, AVX2, no AVX-512)

	tok/s
Before (scalar stub)	~0.04
After (AVX2)	~8.0
Speedup	~200x

The 8 tok/s result is at the compute-bound ceiling for Q1_0_g128 on this CPU — Q1_0_g128 is ~4x more compute-intensive per byte than Q4_0, so further gains would require AVX-512 or a fundamentally different algorithm.