clocks: add V4A family (CV500 / AV300) — 4 PLLs + HPM

[widgetii]

Adds a clocks_family_v4a table covering Hi3516CV500 / Hi3516AV300 / Hi3516DV300 etc. (chip_generation = HISI_V4A = 0x3516C500).

Sources

Register map sourced first-party from:

• widgetii/HI3516CV500-SDK sdk/bootrom/bootrom-re/regmap-crg.h — CRG register-pair offsets (APLL/DPLL/EPLL/VPLL CONFIG_0/1, PLL_LOCK_STAT).
• HI3516CV500-SDK/sdk/fastburn/fastboot/Source/ddr_training.c — HPM register addresses, sys_hpm_core bit layout (9-bit on V4A, not 10-bit like V4), and 150-350 validity clamp.

What's decoded

Section	V4	V4A (this PR)
APLL pair	(CRG+0x00, CRG+0x04)	same
DPLL pair	dumped raw only (#163 dropped)	(CRG+0x08, CRG+0x0C), fully decoded
EPLL pair	dumped raw only (#163 dropped)	(CRG+0x10, CRG+0x14), fully decoded
VPLL pair	dumped raw only (#163 dropped)	(CRG+0x18, CRG+0x1C), fully decoded
PLL lock bit (CPU)	PERI_CRG_PLL122 bit 0	same
PLL lock bits (DPLL/EPLL/VPLL)	not decoded	bits 1 / 3 / 2
HPM_CHECK_REG	0x1202015C (10-bit)	0x12020098 (9-bit)
HPM aux fingerprint	0x120280D8	0x120300D8
DDR cksel mux	0x12010080 + cksel table	not decoded -- bit positions not in the RE; skipped per "decypher or remove" rule from #163

All four PLLs on V4A use the same Hi3516A APLL bit layout (FBDIV at ctrl_reg2[11:0]), unlike V4 where DPLL/EPLL had a different (still-unverified) layout. This is why V4A can decode all four cleanly while V4 still can't.

Brief survey shape

V4A's brief block falls back to 2 headline numbers (CPU clock + HPM bin), since DDR cksel isn't decoded yet:

clocks:
  cpu_pll:
    freq_mhz: 900
  hpm:
    bin: mid

V4 boards still get the same 8-line brief block as in #163 (cpu_pll + ddr.data_rate_mbps + hpm.bin).

Brief-mode tightening (V4A motivated)

The brief-PLL emitter now ships only the first PLL of the family (by convention the CPU/APLL). DPLL/EPLL/VPLL on V4A are detail and only appear in the full ipctool clocks output. V4 brief is unchanged (V4 only has one PLL entry anyway).

Sample full output (openipc-hi3516av300)

clocks:
  cpu_pll:    freq_mhz: 900   locked: true   (FBDIV=75  POSTDIV1=2  POSTDIV2=1)
  ddr_pll:    freq_mhz: 594   locked: true   (FBDIV=99  POSTDIV1=4  POSTDIV2=1)
  eth_pll:    freq_mhz: 528   locked: true   (FBDIV=44  POSTDIV1=2  POSTDIV2=1)
  video_pll:  freq_mhz: 552   locked: true   (FBDIV=46  POSTDIV1=2  POSTDIV2=1)
  hpm:        value: 260      bin: mid       aux_value: 0x81090109

Test plan

• Verified on openipc-hi3516av300.dlab.doty.ru (dual-core Cortex-A7, SMP, Linux 4.9.37):
  • brief: 5 lines after clocks: (cpu_pll.freq_mhz + hpm.bin)
  • full: APLL=900 / DPLL=594 / EPLL=528 / VPLL=552 MHz, all locked: true; HPM value=260 (mid bin), aux=0x81090109
  • ipctool cpubench median = 899 MHz (within 0.1% of register-decoded APLL)
• V4 boards (hi3516ev300 OpenIPC + gk7205v300 OpenIPC) re-verified — same 8-line brief block as merged in clocks: brief survey output, decode APLL lock, drop noisy notes #163, no regression.
• CI baseline build (cv100 toolchain + bare UPX) — no warnings under -Wextra.

Out of scope (TODOs in code comments)

• DDR cksel mux on V4A — needs a board where DDR rate is independently known to anchor the cksel field.
• Confirm the inferred VPLL=bit-2 lock-bit assignment (V4A bootrom RE only references bits 0/1/3 explicitly; bit 2 is inferred from 0x0F readback meaning all four are locked).
• DPLL/EPLL FBDIV decode on V4 (their bit layout differs from V4A; still unanchored).

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