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Merged
arghunter merged 1 commit into from
Mar 13, 2026
Merged

Extra Stage, Pipelined, 50% speed boost #4

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2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
56 changes: 28 additions & 28 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
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Expand Up @@ -1314,11 +1314,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4b09b841</spirit:value>
<spirit:value>9:7df132ee</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1333,11 +1333,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4b09b841</spirit:value>
<spirit:value>9:7df132ee</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1352,11 +1352,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1371,11 +1371,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1386,7 +1386,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1397,7 +1397,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7e84de70</spirit:value>
<spirit:value>9:ea0c8e5a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1411,11 +1411,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:39 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:0455ee43</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1429,11 +1429,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1444,7 +1444,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1460,11 +1460,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:21 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand All @@ -1478,11 +1478,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Mar 13 05:23:22 UTC 2026</spirit:value>
<spirit:value>Fri Mar 13 07:18:52 UTC 2026</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:4111229a</spirit:value>
<spirit:value>9:6e49cf90</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
Expand Down Expand Up @@ -2725,7 +2725,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">clk_out2__100.00000______0.000______50.0______130.958_____98.575</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">clk_out2__200.00000______0.000______50.0______114.829_____98.575</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
Expand Down Expand Up @@ -2753,7 +2753,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">100.000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">200.000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
Expand Down Expand Up @@ -2837,7 +2837,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">100.00000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">200.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
Expand Down Expand Up @@ -3005,7 +3005,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">10</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">5</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
Expand Down Expand Up @@ -3531,7 +3531,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_DIVIDE2_AUTO</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.25</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.125</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_DIVIDE3_AUTO</spirit:name>
Expand Down Expand Up @@ -3639,7 +3639,7 @@
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">100.00000</spirit:value>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">200.00000</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="STRING">
<spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
Expand Down Expand Up @@ -4352,7 +4352,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">200.000</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
Expand Down Expand Up @@ -4688,7 +4688,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">10</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">5</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
Expand Down Expand Up @@ -4997,7 +4997,7 @@
<spirit:parameter>
<spirit:name>CLKOUT2_JITTER</spirit:name>
<spirit:displayName>Clkout2 Jitter</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">130.958</spirit:value>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">114.829</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
Expand Down
4 changes: 2 additions & 2 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
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Expand Up @@ -54,7 +54,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down Expand Up @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0;
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_DIVIDE (5),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
Expand Down
12 changes: 6 additions & 6 deletions ...Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
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Expand Up @@ -2,10 +2,10 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Fri Mar 13 01:23:39 2026
// Date : Fri Mar 13 02:38:01 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode funcsim
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix
// clk_wiz_0_ clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
Expand All @@ -32,15 +32,15 @@ module clk_wiz_0
wire locked;
wire reset;

clk_wiz_0_clk_wiz inst
clk_wiz_0_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.locked(locked),
.reset(reset));
endmodule

module clk_wiz_0_clk_wiz
module clk_wiz_0_clk_wiz_0_clk_wiz
(clk_out1,
clk_out2,
reset,
Expand Down Expand Up @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(10),
.CLKOUT1_DIVIDE(5),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
Expand Down
16 changes: 8 additions & 8 deletions ...ffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
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Expand Up @@ -2,10 +2,10 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Fri Mar 13 01:23:39 2026
-- Date : Fri Mar 13 02:38:01 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix
-- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
Expand All @@ -15,17 +15,17 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0_clk_wiz is
entity clk_wiz_0_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end clk_wiz_0_clk_wiz;
end clk_wiz_0_clk_wiz_0_clk_wiz;

architecture STRUCTURE of clk_wiz_0_clk_wiz is
architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clk_out2_clk_wiz_0 : STD_LOGIC;
Expand Down Expand Up @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 10,
CLKOUT1_DIVIDE => 5,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
Expand Down Expand Up @@ -187,7 +187,7 @@ end clk_wiz_0;

architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0_clk_wiz
inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
Expand Down
6 changes: 3 additions & 3 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
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Expand Up @@ -2,10 +2,10 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Fri Mar 13 01:23:39 2026
// Date : Fri Mar 13 02:38:01 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode synth_stub
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix
// clk_wiz_0_ clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
Expand Down
6 changes: 3 additions & 3 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
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Expand Up @@ -2,10 +2,10 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Fri Mar 13 01:23:39 2026
-- Date : Fri Mar 13 02:38:01 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
-- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix
-- clk_wiz_0_ clk_wiz_0_stub.vhdl
-- Design : clk_wiz_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
Expand Down
2 changes: 1 addition & 1 deletion RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo
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Expand Up @@ -53,7 +53,7 @@
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__25.00000______0.000______50.0______175.402_____98.575
// clk_out2__100.00000______0.000______50.0______130.958_____98.575
// clk_out2__200.00000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand Down
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