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Merged
arghunter merged 3 commits into from
Mar 12, 2026
Merged

Eliminated the VGA DSP #2

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b9a715c
vga addr simplification - 5ns timing imp
arghunter Mar 11, 2026
d74f74d
temp
arghunter Mar 12, 2026
62d9ae2
remove old code
arghunter Mar 12, 2026
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7 changes: 2 additions & 5 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
// clk_out1__25.00000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand All @@ -63,13 +62,12 @@

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)

module clk_wiz_0
(
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
input reset,
output locked,
Expand All @@ -81,7 +79,6 @@ module clk_wiz_0
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
// Status and control signals
.reset(reset),
.locked(locked),
Expand Down
4 changes: 1 addition & 3 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo
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Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
// clk_out1__25.00000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand All @@ -70,7 +69,6 @@
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
.clk_out2(clk_out2), // output clk_out2
// Status and control signals
.reset(reset), // input reset
.locked(locked), // output locked
Expand Down
192 changes: 46 additions & 146 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
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19 changes: 5 additions & 14 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
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Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
// clk_out1__25.00000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand All @@ -68,7 +67,6 @@ module clk_wiz_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
// Status and control signals
input reset,
output locked,
Expand Down Expand Up @@ -109,6 +107,7 @@ wire clk_in2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
Expand All @@ -127,17 +126,13 @@ wire clk_in2_clk_wiz_0;
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_MULT_F (9.125),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (5.000),
.CLKOUT0_DIVIDE_F (36.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (40),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000))
mmcm_adv_inst
// Output clocks
Expand All @@ -146,7 +141,7 @@ wire clk_in2_clk_wiz_0;
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
Expand Down Expand Up @@ -202,10 +197,6 @@ wire clk_in2_clk_wiz_0;
.I (clk_out1_clk_wiz_0));


BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_clk_wiz_0));



endmodule
23 changes: 6 additions & 17 deletions ...Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Wed Mar 11 01:32:49 2026
// Date : Wed Mar 11 16:44:32 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode funcsim
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
Expand All @@ -16,38 +16,32 @@
(* NotValidForBitStream *)
module clk_wiz_0
(clk_out1,
clk_out2,
reset,
locked,
clk_in1);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;

(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire clk_out2;
wire locked;
wire reset;

clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.locked(locked),
.reset(reset));
endmodule

module clk_wiz_0_clk_wiz
(clk_out1,
clk_out2,
reset,
locked,
clk_in1);
output clk_out1;
output clk_out2;
input reset;
output locked;
input clk_in1;
Expand All @@ -56,8 +50,6 @@ module clk_wiz_0_clk_wiz
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clk_out2;
wire clk_out2_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
Expand All @@ -66,6 +58,7 @@ module clk_wiz_0_clk_wiz
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
Expand Down Expand Up @@ -96,22 +89,18 @@ module clk_wiz_0_clk_wiz
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_out2_clk_wiz_0),
.O(clk_out2));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_MULT_F(9.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(5.000000),
.CLKOUT0_DIVIDE_F(36.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
Expand Down Expand Up @@ -160,7 +149,7 @@ module clk_wiz_0_clk_wiz
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_out2_clk_wiz_0),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
Expand Down
21 changes: 6 additions & 15 deletions ...ffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Wed Mar 11 01:32:49 2026
-- Date : Wed Mar 11 16:44:32 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
Expand All @@ -18,7 +18,6 @@ use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
Expand All @@ -28,13 +27,13 @@ end clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clk_out2_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
Expand All @@ -56,7 +55,6 @@ architecture STRUCTURE of clk_wiz_0_clk_wiz is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
Expand All @@ -77,24 +75,19 @@ clkout1_buf: unisim.vcomponents.BUFG
I => clk_out1_clk_wiz_0,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_clk_wiz_0,
O => clk_out2
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 5.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 40,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
Expand Down Expand Up @@ -144,7 +137,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_out2_clk_wiz_0,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
Expand Down Expand Up @@ -176,7 +169,6 @@ use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
Expand All @@ -191,7 +183,6 @@ inst: entity work.clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2,
locked => locked,
reset => reset
);
Expand Down
10 changes: 4 additions & 6 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
// Date : Wed Mar 11 01:32:49 2026
// Date : Wed Mar 11 16:44:32 2026
// Host : arya running 64-bit EndeavourOS Linux
// Command : write_verilog -force -mode synth_stub
// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
Expand All @@ -14,13 +14,11 @@
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1)
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0(clk_out1, reset, locked, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
/* synthesis syn_force_seq_prim="clk_out1" */
/* synthesis syn_force_seq_prim="clk_out2" */;
/* synthesis syn_force_seq_prim="clk_out1" */;
output clk_out1 /* synthesis syn_isclock = 1 */;
output clk_out2 /* synthesis syn_isclock = 1 */;
input reset;
output locked;
input clk_in1;
Expand Down
7 changes: 3 additions & 4 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
-- Date : Wed Mar 11 01:32:49 2026
-- Date : Wed Mar 11 16:44:32 2026
-- Host : arya running 64-bit EndeavourOS Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
Expand All @@ -16,20 +16,19 @@ use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_0 is
Port (
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);

attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_0;

architecture stub of clk_wiz_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1";
attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
begin
end;
4 changes: 1 addition & 3 deletions RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo
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Expand Up @@ -52,8 +52,7 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__200.00000______0.000______50.0______114.829_____98.575
// clk_out2__25.00000______0.000______50.0______175.402_____98.575
// clk_out1__25.00000______0.000______50.0______181.828____104.359
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
Expand All @@ -70,7 +69,6 @@
(
// Clock out ports
.clk_out1(clk_out1), // output clk_out1
.clk_out2(clk_out2), // output clk_out2
// Status and control signals
.reset(reset), // input reset
.locked(locked), // output locked
Expand Down
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