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@jannau jannau commented Dec 7, 2025

Adds chickens, midr and bringup UART address and refactors dapf parsing

Fixes: eedaf29 ("m1n1.setup: Always reset PMU boot error counters")
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
0x40 from "dart-options" does not identify the layout. T8122's dart-pmp
has this set but uses in macOS 26.0.1 the 52 byte descriptor layout.
Since this is not used in python code just simplify the parsing so that
it does not fall over.

Signed-off-by: Janne Grunau <j@jannau.net>
T8122's dart-pmp dapf-instance-0 has no fixed layout. At least up to
macOS 15.1 it uses a 56 byte layout (DAPFT8110B in m1n1/adt.py) and
macOS 26.0.1 switches to the standard 52 byte layout. The flag from
"dart-options" used in m1n1/adt.py does not distinguish these two
variants.
Support both variants and prefer the original 52 byte variant. The
array length does not identify the variant for multiples of 728. This
actually occurs on t8122's dart-aop.dapf-instance-0 and the 52 byte
variant is correct in that case.

Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
Signed-off-by: Janne Grunau <j@jannau.net>
@jannau jannau requested a review from svenpeter42 as a code owner December 7, 2025 13:49
#elif TARGET == T8132
#define EARLY_UART_BASE 0x3ad200000
#elif TARGET == T8122
#define EARLY_UART_BASE 0x2a1200000
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Duplicate UART base

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this should be fixed though :)

reg_clr(s3_0_c15_c2_4, BIT(0) | BIT(1) | BIT(16) | BIT(17) | BIT(18) | BIT(22));
}

void init_t8122_everest(int rev)
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@asdfugil asdfugil Dec 7, 2025

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There is a init_common_everest() function, it should be used.

init_t6030_everest() already have the duplication problem so maybe modify that one to use init_common_everest() as well.

in init_common_everest(), s3_0_c15_c2_3 and s3_0_c15_c2_4 appears to be HID30 and HID31 respectively.

P.S. t6031's init sequence specifically touches 1 GHz/24 MHz timer related registers s3_1_c15_c1_5 (AGTCNTRDIR_EL1) and s3_4_c15_c14_6 (AGTCNTRDIR_EL12) when the whole M3-series has them but given the state of things for this PR it's fine to leave that as is and change them later.

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imho it's chicken bits and at least I don't care about duplication here as long as they work.

reg_clr(s3_0_c15_c2_4, BIT(0) | BIT(1) | BIT(16) | BIT(17) | BIT(18) | BIT(22));
}

void init_t8122_everest(int rev)
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imho it's chicken bits and at least I don't care about duplication here as long as they work.

#elif TARGET == T8132
#define EARLY_UART_BASE 0x3ad200000
#elif TARGET == T8122
#define EARLY_UART_BASE 0x2a1200000
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this should be fixed though :)

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3 participants