Update core_cm33.h

[AlbertHuang-CPU]

Add SFSR and SFAR in SCB_Type.

[JonatanAntoni]

Hi @AlbertHuang-CPU,

We checked the header for these registers and it looks like they are already part of the SAU_Type. This is aligned with the Arm®v8-M Architecture Reference Manual.

Is it a fair statement that is should be enough to have the registers defined there? Or are there any specific requirements to have the registers being part of the SCB_Type in addition?

Thanks,
Jonatan

[AlbertHuang-CPU]

Hi Jonatan, In Arm v8m definition, the address is just in the SCB scope. ***@***.***D77E62.79588C60]  In practical, SAU can be configured out, and be taken over by implementation defined IDAU. That means although there is no SAU, the secure fault still possible happens and the SFSR still need to be accessed. Regards, Albert From: Jonatan Antoni ***@***.***> Sent: Wednesday, July 21, 2021 6:18 PM To: ARM-software/CMSIS_5 ***@***.***> Cc: Albert Huang ***@***.***>; Mention ***@***.***> Subject: Re: [ARM-software/CMSIS_5] Update core_cm33.h (#1255) Hi @AlbertHuang-CPU<https://github.com/AlbertHuang-CPU>, We checked the header for these registers and it looks like they are already part of the SAU_Type. This is aligned with the Arm®v8-M Architecture Reference Manual. Is it a fair statement that is should be enough to have the registers defined there? Or are there any specific requirements to have the registers being part of the SCB_Type in addition? Thanks, Jonatan — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub<#1255 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AN45N2XAYEIXY3NA7M3LMMLTY2NFFANCNFSM5AXTPCWQ>.