DRAM Controller

A high-performance modular Verilog SDRAM controller (v3.0.0) with page hit optimization for up to 60% faster sequential access. Implements full SDRAM protocol with configurable timing, bank addressing, and intelligent row management.

🚀 New in v3.0 - Performance Optimizations

Page Hit/Miss Detection

• Open Row Policy: Keeps rows open after access for faster subsequent operations
• Page Hit: Same row/bank access → ~3-4 cycles (60% faster than v2.0)
• Page Miss: Different row → Auto precharge and activate
• Smart Precharge: Only closes rows when necessary (refresh or different row)

Bank Address Support

• 4-Bank Architecture: Independent row management per bank (2-bit bank address)
• 24-bit Addressing: [23:22] Bank | [21:9] Row | [8:0] Column
• SDRAM Compatible: Standard JEDEC SDRAM signaling with dram_ba[1:0]

Performance Improvements

Access Pattern	v2.0 Latency	v3.0 Latency	Speedup
Sequential	7 cycles	3-4 cycles	~57%
Block 256B	896 cycles	391 cycles	~56%
Random	7 cycles	4.5 cycles	~36%

See ENHANCEMENTS.md for detailed technical analysis.

Key Features

• Modular Design: 6 focused RTL modules + utils and testbench
• Full SDRAM Protocol: ACTIVATE/READ/WRITE/PRECHARGE/AUTO-REFRESH
• Page Hit Optimization: Intelligent row management for reduced latency
• Bank Addressing: 4-bank support with independent row tracking
• Configurable Timing: tRCD, tRP, tCAS, tRAS, tRC, tREF
• Comprehensive Testing: Testbench with page hit/miss verification
• Parameterizable: Flexible DRAM sizes and bus widths

Project Layout

dram-controller/
├── rtl/
│   ├── dram_controller_top.v      # Top-level integration + CPU interface
│   ├── core/
│   │   ├── dram_fsm.v             # State machine (with page hit logic)
│   │   ├── dram_command_generator.v  # SDRAM signal generator
│   │   └── refresh_controller.v   # Periodic refresh management
│   └── utils/
│       ├── address_decoder.v      # Bank/row/column decomposition
│       ├── timing_generator.v     # Timing countdown logic
│       └── dram_pkg.vh            # Shared parameters
├── tb/
│   ├── dram_controller_tb.v       # Comprehensive testbench
│   └── dram_model_simple.v        # Behavioral DRAM model
├── docs/
│   ├── GETTING_STARTED.md
│   ├── architecture.md
│   └── QUICK_REFERENCE.md         # Code snippets and debug tips
├── scripts/
│   ├── simulate.bat/.ps1/.sh      # Simulation scripts
├── ENHANCEMENTS.md                # v3.0 technical details
└── README.md

Core Modules

dram_controller_top

• Integration layer connecting all submodules
• CPU interface: address, data, read/write requests
• DRAM interface: RAS/CAS/WE/CS/CKE + bank address

address_decoder

• Decomposes 24-bit address into bank (2b), row (13b), column (9b)
• Latches addresses during operations

dram_fsm (Enhanced in v3.0)

• Main state machine with page hit/miss detection
• Tracks open row per bank for optimization
• Intelligent state transitions: IDLE → ACTIVATE → READ/WRITE → IDLE (row open)
• Priority: Refresh > Page Hit > Page Miss

dram_command_generator

• Generates DRAM control signals (RAS, CAS, WE, CS, CKE, BA)
• Multiplexes row/column addresses
• Controls bidirectional data bus

refresh_controller

• Periodic refresh request generation
• Row counter for distributed refresh
• Configurable refresh interval

timing_generator

• Provides precise timing delays for DRAM operations
• Selectable timing modes (tRCD, tRP, tCAS, etc.)

Quick Start

Prerequisites

• Icarus Verilog (iverilog) for simulation
• GTKWave for waveform viewing (optional)

Run Simulation

# Windows PowerShell
.\scripts\simulate.ps1

# Windows CMD
.\scripts\simulate.bat

# Linux/Mac
./scripts/simulate.sh

Manual Compilation

iverilog -g2012 -o sim_output/dram_controller_sim.vvp \
  rtl/utils/dram_pkg.vh \
  rtl/utils/*.v \
  rtl/core/*.v \
  rtl/dram_controller_top.v \
  tb/*.v

vvp sim_output/dram_controller_sim.vvp
gtkwave sim_output/dram_controller.vcd

Testing

Testbench Coverage

• ✅ Reset and initialization
• ✅ Single write/read operations
• ✅ Page Hit Test: Sequential access to same row (3-4 cycles)
• ✅ Page Miss Test: Access to different row (auto precharge)
• ✅ Multi-Bank Test: Independent bank operations
• ✅ Refresh cycle observation
• ✅ Data integrity verification
• ✅ Pass/fail reporting

Example Test Output

========================================
  DRAM Controller Testbench
========================================

=== Page Hit Test (Same Row Access) ===
[150] TEST #5: Write - Addr=0x010000, Data=0xAAAA
[220] Write complete

[230] TEST #6: Write - Addr=0x010001, Data=0xBBBB (PAGE HIT!)
[270] Write complete  (40ns instead of 70ns!)

========================================
  Test Summary
========================================
Total Tests: 20
Passed: 20
Failed: 0
*** ALL TESTS PASSED ***

Configuration

Default Parameters

BANK_ADDR_WIDTH = 2      // 4 banks
ROW_ADDR_WIDTH = 13      // 8192 rows per bank
COL_ADDR_WIDTH = 9       // 512 columns
DATA_WIDTH = 16          // 16-bit data bus
Total Addressable: 16MB

Timing Parameters (example for 100MHz clock)

T_RCD = 2   // Row-to-Column Delay (20ns)
T_RP  = 2   // Row Precharge Time (20ns)
T_CAS = 3   // Column Access Strobe (30ns)
T_REF = 780 // Refresh interval (7.8μs)

Documentation

• ENHANCEMENTS.md - v3.0 page hit optimization details
• docs/QUICK_REFERENCE.md - Code snippets and debugging
• docs/GETTING_STARTED.md - Setup and integration guide
• docs/architecture.md - Detailed architecture documentation

Performance Tips

Best Performance (Page Hits)

• Sequential memory access
• Array processing
• Cache line fills
• Video frame buffers

Expected Speedup

• Sequential operations: 50-60% faster
• Block transfers: 50-60% faster
• Mixed workload: 30-40% faster
• Random access: Neutral to 12% slower

License

MIT License - See LICENSE for details

Version History

• v3.0.0 (December 2025) - Page hit optimization, bank addressing, performance enhancements
• v2.0.0 (November 2025) - Modular architecture, comprehensive testing
• v1.0.0 - Initial release

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Version: 3.0.0 — Last updated December 2025