diff --git a/.github/workflows/boards.yml b/.github/workflows/boards.yml index d06462f..b36ee8e 100644 --- a/.github/workflows/boards.yml +++ b/.github/workflows/boards.yml @@ -11,7 +11,7 @@ jobs: runs-on: ubuntu-latest strategy: matrix: - board: [stm32wb55xx_nucleo, stm32wba55cg_nucleo, pic32cz_curiosity_ultra, stm32h563zi_nucleo, stm32f411_blackpill, stm32c031_nucleo, stm32f091rc_nucleo, stm32f302r8_nucleo, stm32l152re_nucleo, stm32n657a0_nucleo] + board: [stm32wb55xx_nucleo, stm32wba55cg_nucleo, pic32cz_curiosity_ultra, stm32h563zi_nucleo, stm32f411_blackpill, stm32c031_nucleo, stm32f091rc_nucleo, stm32f302r8_nucleo, stm32l152re_nucleo, stm32n657a0_nucleo, stm32u5a5zj_nucleo] extra_cflags: ["", "-DWHAL_CFG_NO_TIMEOUT"] include: - board: stm32wb55xx_nucleo diff --git a/.github/workflows/watchdog-tests.yml b/.github/workflows/watchdog-tests.yml index be1a417..d4cc717 100644 --- a/.github/workflows/watchdog-tests.yml +++ b/.github/workflows/watchdog-tests.yml @@ -18,6 +18,10 @@ jobs: watchdog: wwdg - board: stm32f091rc_nucleo watchdog: iwdg + - board: stm32u5a5zj_nucleo + watchdog: iwdg + - board: stm32u5a5zj_nucleo + watchdog: wwdg steps: - uses: actions/checkout@v4 diff --git a/boards/README.md b/boards/README.md index c433294..b1ce88b 100644 --- a/boards/README.md +++ b/boards/README.md @@ -23,6 +23,7 @@ build configuration. | ST NUCLEO-WB55RG | STM32WB | Cortex-M4 | `stm32wb55xx_nucleo/` | | ST NUCLEO-L152RE | STM32L1 | Cortex-M3 | `stm32l152re_nucleo/` | | ST NUCLEO-N657X0-Q | STM32N6 | Cortex-M55 | `stm32n657a0_nucleo/` | +| ST NUCLEO-U5A5ZJ-Q | STM32U5 | Cortex-M33 | `stm32u5a5zj_nucleo/` | | ST NUCLEO-WBA55CG | STM32WBA | Cortex-M33 | `stm32wba55cg_nucleo/` | ## Board Directory Contents diff --git a/boards/stm32c031_nucleo/board.h b/boards/stm32c031_nucleo/board.h index 0439815..76d2e95 100644 --- a/boards/stm32c031_nucleo/board.h +++ b/boards/stm32c031_nucleo/board.h @@ -68,7 +68,7 @@ enum { } /* GPIO dev initializer — singleton defined in stm32wb_gpio.c (shared driver). */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32C0_GPIO_DEV { \ .base = WHAL_STM32C031_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32c0_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32c0_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32f091rc_nucleo/board.h b/boards/stm32f091rc_nucleo/board.h index 4be5510..63c8f16 100644 --- a/boards/stm32f091rc_nucleo/board.h +++ b/boards/stm32f091rc_nucleo/board.h @@ -76,7 +76,7 @@ enum { /* IWDG dev initializer — singleton defined in stm32wb_iwdg.c * (the stm32f0_iwdg.c source is an include alias). */ -#define WHAL_CFG_STM32WB_IWDG_DEV { \ +#define WHAL_CFG_STM32F0_IWDG_DEV { \ .base = WHAL_STM32F091_IWDG_BASE, \ .cfg = (void *)&(const whal_Stm32f0_Iwdg_Cfg){ \ .prescaler = WHAL_STM32F0_IWDG_PR_64, \ @@ -97,7 +97,7 @@ enum { } /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32F0_GPIO_DEV { \ .base = WHAL_STM32F091_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32f0_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32f0_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32f302r8_nucleo/board.h b/boards/stm32f302r8_nucleo/board.h index 8a3a37e..53d4d75 100644 --- a/boards/stm32f302r8_nucleo/board.h +++ b/boards/stm32f302r8_nucleo/board.h @@ -66,7 +66,7 @@ enum { /* WWDG dev initializer — singleton defined in stm32f0_wwdg.c (stm32f3 * is an include alias). Compiled unconditionally because the .c always * references it. */ -#define WHAL_CFG_STM32F0_WWDG_DEV { \ +#define WHAL_CFG_STM32F3_WWDG_DEV { \ .base = WHAL_STM32F302_WWDG_BASE, \ .cfg = (void *)&(const whal_Stm32f3_Wwdg_Cfg){ \ .prescaler = 3, \ @@ -77,7 +77,7 @@ enum { /* IWDG dev initializer — singleton defined in stm32wb_iwdg.c (stm32f3 is * an include alias). */ -#define WHAL_CFG_STM32WB_IWDG_DEV { \ +#define WHAL_CFG_STM32F3_IWDG_DEV { \ .base = WHAL_STM32F302_IWDG_BASE, \ .cfg = (void *)&(const whal_Stm32f3_Iwdg_Cfg){ \ .prescaler = WHAL_STM32F3_IWDG_PR_64, \ @@ -88,7 +88,7 @@ enum { /* Flash dev initializer — singleton defined in stm32f0_flash.c (stm32f3 is * an include alias). */ -#define WHAL_CFG_STM32F0_FLASH_DEV { \ +#define WHAL_CFG_STM32F3_FLASH_DEV { \ .driver = WHAL_STM32F302_FLASH_DRIVER, \ .base = WHAL_STM32F302_FLASH_BASE, \ .cfg = (void *)&(const whal_Stm32f3_Flash_Cfg){ \ @@ -99,7 +99,7 @@ enum { } /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32F3_GPIO_DEV { \ .base = WHAL_STM32F302_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32f3_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32f3_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32f411_blackpill/board.h b/boards/stm32f411_blackpill/board.h index 9e40712..95fc8b3 100644 --- a/boards/stm32f411_blackpill/board.h +++ b/boards/stm32f411_blackpill/board.h @@ -75,7 +75,7 @@ extern const whal_Stm32f4_Flash_Sector g_flashSectors[FLASH_SECTOR_COUNT]; } /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32F4_GPIO_DEV { \ .base = WHAL_STM32F411_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32f4_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32f4_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32h563zi_nucleo/board.h b/boards/stm32h563zi_nucleo/board.h index 30648b6..e2fb1d2 100644 --- a/boards/stm32h563zi_nucleo/board.h +++ b/boards/stm32h563zi_nucleo/board.h @@ -79,7 +79,7 @@ enum { /* GPIO singleton — referenced by stm32wb_gpio.c directly. */ /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32H5_GPIO_DEV { \ .base = WHAL_STM32H563_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32h5_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32h5_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32l152re_nucleo/board.h b/boards/stm32l152re_nucleo/board.h index 0797bd7..28e27e9 100644 --- a/boards/stm32l152re_nucleo/board.h +++ b/boards/stm32l152re_nucleo/board.h @@ -67,7 +67,7 @@ enum { /* WWDG dev initializer — singleton defined in stm32f0_wwdg.c (stm32l1 is * an include alias). Compiled unconditionally because the .c always * references it. */ -#define WHAL_CFG_STM32F0_WWDG_DEV { \ +#define WHAL_CFG_STM32L1_WWDG_DEV { \ .base = WHAL_STM32L152_WWDG_BASE, \ .cfg = (void *)&(const whal_Stm32l1_Wwdg_Cfg){ \ .prescaler = 3, \ @@ -78,7 +78,7 @@ enum { /* IWDG dev initializer — singleton defined in stm32wb_iwdg.c (stm32l1 is * an include alias). */ -#define WHAL_CFG_STM32WB_IWDG_DEV { \ +#define WHAL_CFG_STM32L1_IWDG_DEV { \ .base = WHAL_STM32L152_IWDG_BASE, \ .cfg = (void *)&(const whal_Stm32l1_Iwdg_Cfg){ \ .prescaler = WHAL_STM32L1_IWDG_PR_64, \ @@ -99,7 +99,7 @@ enum { } /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32L1_GPIO_DEV { \ .base = WHAL_STM32L152_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32l1_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32l1_Gpio_PinCfg[PIN_COUNT]){ \ diff --git a/boards/stm32n657a0_nucleo/board.h b/boards/stm32n657a0_nucleo/board.h index 5b4eb13..e8a0708 100644 --- a/boards/stm32n657a0_nucleo/board.h +++ b/boards/stm32n657a0_nucleo/board.h @@ -97,7 +97,7 @@ enum { /* IWDG/WWDG dev initializers — singletons defined in stm32wb_iwdg.c / * stm32wb_wwdg.c (stm32n6 is an include alias). */ -#define WHAL_CFG_STM32WB_IWDG_DEV { \ +#define WHAL_CFG_STM32N6_IWDG_DEV { \ .base = WHAL_STM32N657_IWDG_BASE, \ .cfg = (void *)&(const whal_Stm32n6_Iwdg_Cfg){ \ .prescaler = WHAL_STM32N6_IWDG_PR_32, \ @@ -106,7 +106,7 @@ enum { }, \ } -#define WHAL_CFG_STM32WB_WWDG_DEV { \ +#define WHAL_CFG_STM32N6_WWDG_DEV { \ .base = WHAL_STM32N657_WWDG_BASE, \ .cfg = (void *)&(const whal_Stm32n6_Wwdg_Cfg){ \ .prescaler = WHAL_STM32N6_WWDG_TB_128, \ @@ -116,7 +116,7 @@ enum { } /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32N6_GPIO_DEV { \ .base = WHAL_STM32N657_GPIO_BASE, \ .cfg = (void *)&(const whal_Stm32n6_Gpio_Cfg){ \ .pinCfg = (const whal_Stm32n6_Gpio_PinCfg[PIN_COUNT]){ \ @@ -217,7 +217,7 @@ enum { /* RNG dev initializer — singleton defined in stm32wba_rng.c (stm32n6 is * an include alias). */ -#define WHAL_CFG_STM32WBA_RNG_DEV { \ +#define WHAL_CFG_STM32N6_RNG_DEV { \ .base = WHAL_STM32N657_RNG_BASE, \ .cfg = (void *)&(const whal_Stm32n6_Rng_Cfg){ \ .timeout = &g_whalTimeout, \ @@ -258,34 +258,34 @@ enum { /* HASH + algorithm dev initializers — singletons defined in stm32wba_hash.c * (stm32n6 is an include alias). */ -#define WHAL_CFG_STM32WBA_HASH_DEV { \ +#define WHAL_CFG_STM32N6_HASH_DEV { \ .base = WHAL_STM32N657_HASH_BASE, \ .cfg = (void *)&(const whal_Stm32n6_Hash_Cfg){ \ .timeout = &g_whalTimeout, \ }, \ } -#define WHAL_CFG_STM32WBA_HASH_SHA1_DEV { \ +#define WHAL_CFG_STM32N6_HASH_SHA1_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } -#define WHAL_CFG_STM32WBA_HASH_SHA224_DEV { \ +#define WHAL_CFG_STM32N6_HASH_SHA224_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } -#define WHAL_CFG_STM32WBA_HASH_SHA256_DEV { \ +#define WHAL_CFG_STM32N6_HASH_SHA256_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } -#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DEV { \ +#define WHAL_CFG_STM32N6_HASH_HMAC_SHA1_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } -#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DEV { \ +#define WHAL_CFG_STM32N6_HASH_HMAC_SHA224_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } -#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DEV { \ +#define WHAL_CFG_STM32N6_HASH_HMAC_SHA256_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wba_Hash_Dev, \ } diff --git a/boards/stm32u5a5zj_nucleo/board.c b/boards/stm32u5a5zj_nucleo/board.c new file mode 100644 index 0000000..22fa29f --- /dev/null +++ b/boards/stm32u5a5zj_nucleo/board.c @@ -0,0 +1,400 @@ +/* board.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +/* Board configuration for the STM32U5A5ZJ Nucleo (modelled on NUCLEO-U5A5ZJ-Q). */ + +#include +#include +#include "board.h" +#include +#include "peripheral.h" + +/* SysTick timing */ +volatile uint32_t g_tick = 0; + +void SysTick_Handler(void) +{ + g_tick++; +} + +uint32_t Board_GetTick(void) +{ + return g_tick; +} + +whal_Timeout g_whalTimeout = { + .timeoutTicks = 1000, /* 1s timeout */ + .GetTick = Board_GetTick, +}; + +/* Clock: PLL1 from HSI16, targeting 160 MHz (max with EPOD booster). + * HSI16 = 16 MHz + * PLL1M = 1 -> ref_ck = 16 MHz + * PLL1N = 20 -> VCO = 16 * 20 = 320 MHz + * PLL1R = 2 -> pll1rclk = 160 MHz + * PLL1RGE = 3 (8-16 MHz range) + * PLL1MBOOST = 0 (bypass — EPOD input = PLL1 input) + */ +static const whal_Stm32u5_Rcc_PeriphClk g_flashClock = {WHAL_STM32U5A5_FLASH_CLOCK}; + +static const whal_Stm32u5_Rcc_PeriphClk g_periphClks[] = { + {WHAL_STM32U5A5_GPIOA_CLOCK}, + {WHAL_STM32U5A5_GPIOB_CLOCK}, + {WHAL_STM32U5A5_GPIOC_CLOCK}, + {WHAL_STM32U5A5_USART1_CLOCK}, + {WHAL_STM32U5A5_SPI1_CLOCK}, + {WHAL_STM32U5A5_RNG_CLOCK}, + {WHAL_STM32U5A5_AES_CLOCK}, + {WHAL_STM32U5A5_HASH_CLOCK}, + {WHAL_STM32U5A5_I2C1_CLOCK}, +#ifdef BOARD_WATCHDOG_WWDG + {WHAL_STM32U5A5_WWDG_CLOCK}, +#endif +}; +#define PERIPH_CLK_COUNT (sizeof(g_periphClks) / sizeof(g_periphClks[0])) + +/* I2C */ +whal_I2c g_whalI2c = { + .base = WHAL_STM32U5A5_I2C1_BASE, + .driver = WHAL_STM32U5A5_I2C1_DRIVER, + + .cfg = &(whal_Stm32u5_I2c_Cfg) { + .pclk = 160000000, + .timeout = &g_whalTimeout, + }, +}; + +/* SPI */ +whal_Spi g_whalSpi = { + .base = WHAL_STM32U5A5_SPI1_BASE, + .driver = WHAL_STM32U5A5_SPI1_DRIVER, + + .cfg = &(whal_Stm32u5_Spi_Cfg) { + .pclk = 160000000, + .timeout = &g_whalTimeout, + }, +}; + +/* DMA */ +#ifdef BOARD_DMA + +whal_Dma g_whalDma1 = { + .base = WHAL_STM32U5A5_GPDMA1_BASE, + .driver = WHAL_STM32U5A5_GPDMA1_DRIVER, + .cfg = &(whal_Stm32u5_Gpdma_Cfg){ + .numChannels = 8, + .timeout = &g_whalTimeout, + }, +}; + +static const whal_Stm32u5_Rcc_PeriphClk g_dmaClock = {WHAL_STM32U5A5_GPDMA1_CLOCK}; + +void GPDMA1_Channel0_IRQHandler(void) +{ + whal_Stm32u5_Gpdma_IRQHandler(&g_whalDma1, 0, NULL, NULL); +} + +void GPDMA1_Channel1_IRQHandler(void) +{ + whal_Stm32u5_Gpdma_IRQHandler(&g_whalDma1, 1, NULL, NULL); +} +#endif + +/* UART (USART1 via VCP at 115200 baud) */ +whal_Uart g_whalUart = { + .base = WHAL_STM32U5A5_USART1_BASE, + .driver = WHAL_STM32U5A5_USART1_DRIVER, + + .cfg = &(whal_Stm32u5_Uart_Cfg) { + .timeout = &g_whalTimeout, + .brr = WHAL_STM32U5_UART_BRR(160000000, 115200), + }, +}; + +/* RNG, AES + mode, HASH + algorithm singletons are defined in their driver TUs + * from WHAL_CFG_* initializers in board.h. */ + +/* Hash (HASH hardware accelerator) — vtable dispatcher for whal_Crypto_Init/Deinit. */ +whal_Crypto g_whalHash = { + .base = WHAL_STM32U5A5_HASH_BASE, + .driver = &whal_Stm32u5_Hash_CryptoDriver, + + .cfg = &(whal_Stm32u5_Hash_Cfg) { + .timeout = &g_whalTimeout, + }, +}; + +#ifdef BOARD_WATCHDOG_IWDG +whal_Watchdog g_whalWatchdog = { + .base = WHAL_STM32U5A5_IWDG_BASE, + .driver = WHAL_STM32U5A5_IWDG_DRIVER, + + .cfg = &(whal_Stm32u5_Iwdg_Cfg) { + .prescaler = WHAL_STM32U5_IWDG_PR_32, + .reload = 100, + .timeout = &g_whalTimeout, + }, +}; +#elif defined(BOARD_WATCHDOG_WWDG) +whal_Watchdog g_whalWatchdog = { + .base = WHAL_STM32U5A5_WWDG_BASE, + .driver = WHAL_STM32U5A5_WWDG_DRIVER, + + .cfg = &(whal_Stm32u5_Wwdg_Cfg) { + .prescaler = WHAL_STM32U5_WWDG_TB_128, + .window = 0x7F, + .counter = 0x7F, + }, +}; +#endif + +void Board_WaitMs(size_t ms) +{ + uint32_t startCount = g_tick; + while (g_tick - startCount < ms); +} + +whal_Error Board_Init(void) +{ + whal_Error err; + + /* Enable PWR clock (RCC_AHB3ENR bit 2) — required to access PWR registers. */ + static const whal_Stm32u5_Rcc_PeriphClk pwrClock = {WHAL_STM32U5A5_PWR_CLOCK}; + err = whal_Stm32u5_Rcc_EnablePeriphClk(&pwrClock); + if (err) + return err; + + /* Switch to voltage scaling Range 1 BEFORE raising SYSCLK above 24 MHz. */ + err = whal_Stm32u5_Pwr_SetVosRange(WHAL_STM32U5_PWR_VOS_RANGE_1); + if (err) + return err; + + /* HSI16 -> PLL1 (M=1, N=20, R=2 -> 160 MHz) -> SYSCLK = PLL1 */ + err = whal_Stm32u5_Rcc_EnableOsc( + &(whal_Stm32u5_Rcc_OscCfg){WHAL_STM32U5_RCC_HSI16_CFG}); + if (err) + return err; + err = whal_Stm32u5_Rcc_EnablePll1(&(whal_Stm32u5_Rcc_Pll1Cfg){ + .clkSrc = WHAL_STM32U5_RCC_PLL1SRC_HSI16, + .rge = WHAL_STM32U5_RCC_PLL1RGE_8_16, + .m = 1, /* /1 -> ref = 16 MHz */ + .mboost = 0, /* bypass EPOD prescaler */ + .n = 20, /* x20 -> VCO = 320 MHz */ + .r = 2, /* /2 -> SYSCLK = 160 MHz */ + .q = 2, + .p = 2, + }); + if (err) + return err; + + /* EPOD booster is required for SYSCLK above 55 MHz in Range 1. */ + err = whal_Stm32u5_Pwr_EnableEpodBooster(); + if (err) + return err; + + /* Enable flash clock and set latency before increasing clock speed. + * At 160 MHz, 3.3 V: 4 wait states required (RM0456 Table 36). */ + err = whal_Stm32u5_Rcc_EnablePeriphClk(&g_flashClock); + if (err) + return err; + + err = whal_Stm32u5_Flash_Ext_SetLatency(BOARD_FLASH_DEV, 4); + if (err) + return err; + + err = whal_Stm32u5_Rcc_SetSysClock(WHAL_STM32U5_RCC_SYSCLK_SRC_PLL1); + if (err) + return err; + +#ifdef BOARD_WATCHDOG_IWDG + /* Enable LSI oscillator required by IWDG */ + err = whal_Stm32u5_Rcc_EnableLsi(); + if (err) + return err; +#endif + + /* Select HSI16 as RNG kernel clock source. */ + err = whal_Stm32u5_Rcc_SetRngClockSrc(WHAL_STM32U5_RCC_RNGSEL_HSI16); + if (err) + return err; + + /* Enable peripheral clocks */ + for (size_t i = 0; i < PERIPH_CLK_COUNT; i++) { + err = whal_Stm32u5_Rcc_EnablePeriphClk(&g_periphClks[i]); + if (err) + return err; + } + + err = whal_Irq_Init(WHAL_INTERNAL_DEV); + if (err) + return err; + +#ifdef BOARD_DMA + err = whal_Stm32u5_Rcc_EnablePeriphClk(&g_dmaClock); + if (err) + return err; + err = whal_Dma_Init(&g_whalDma1); + if (err) + return err; + + /* Enable NVIC interrupts for GPDMA1 channel 0 (IRQ 27) and channel 1 (IRQ 28). */ + err = whal_Irq_Enable(WHAL_INTERNAL_DEV, 27, NULL); + if (err) + return err; + err = whal_Irq_Enable(WHAL_INTERNAL_DEV, 28, NULL); + if (err) + return err; +#endif + + err = whal_Gpio_Init(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Uart_Init(&g_whalUart); + if (err) + return err; + + err = whal_Spi_Init(&g_whalSpi); + if (err) + return err; + + err = whal_I2c_Init(&g_whalI2c); + if (err) + return err; + + err = whal_Flash_Init(BOARD_FLASH_DEV); + if (err) + return err; + + err = whal_Rng_Init(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Crypto_Init(&g_whalHash); + if (err) + return err; + + err = whal_Timer_Init(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Timer_Start(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = Peripheral_Init(); + if (err) + return err; + + return WHAL_SUCCESS; +} + +whal_Error Board_Deinit(void) +{ + whal_Error err; + + err = Peripheral_Deinit(); + if (err) + return err; + + err = whal_Timer_Stop(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Timer_Deinit(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Crypto_Deinit(&g_whalHash); + if (err) + return err; + + err = whal_Rng_Deinit(WHAL_INTERNAL_DEV); + if (err) + return err; + + err = whal_Flash_Deinit(BOARD_FLASH_DEV); + if (err) + return err; + + err = whal_I2c_Deinit(&g_whalI2c); + if (err) + return err; + + err = whal_Spi_Deinit(&g_whalSpi); + if (err) + return err; + + err = whal_Uart_Deinit(&g_whalUart); + if (err) + return err; + + err = whal_Gpio_Deinit(WHAL_INTERNAL_DEV); + if (err) + return err; + +#ifdef BOARD_DMA + whal_Irq_Disable(WHAL_INTERNAL_DEV, 27); + whal_Irq_Disable(WHAL_INTERNAL_DEV, 28); + + err = whal_Dma_Deinit(&g_whalDma1); + if (err) + return err; + err = whal_Stm32u5_Rcc_DisablePeriphClk(&g_dmaClock); + if (err) + return err; +#endif + + err = whal_Irq_Deinit(WHAL_INTERNAL_DEV); + if (err) + return err; + + /* Disable peripheral clocks */ + for (size_t i = 0; i < PERIPH_CLK_COUNT; i++) { + err = whal_Stm32u5_Rcc_DisablePeriphClk(&g_periphClks[i]); + if (err) + return err; + } + +#ifdef BOARD_WATCHDOG_IWDG + err = whal_Stm32u5_Rcc_DisableLsi(); + if (err) + return err; +#endif + + err = whal_Stm32u5_Rcc_SetSysClock(WHAL_STM32U5_RCC_SYSCLK_SRC_HSI16); + if (err) + return err; + err = whal_Stm32u5_Rcc_DisablePll1(); + if (err) + return err; + + /* Reduce flash latency then disable flash clock */ + err = whal_Stm32u5_Flash_Ext_SetLatency(BOARD_FLASH_DEV, 0); + if (err) + return err; + + err = whal_Stm32u5_Rcc_DisablePeriphClk(&g_flashClock); + if (err) + return err; + + return WHAL_SUCCESS; +} diff --git a/boards/stm32u5a5zj_nucleo/board.h b/boards/stm32u5a5zj_nucleo/board.h new file mode 100644 index 0000000..c11f654 --- /dev/null +++ b/boards/stm32u5a5zj_nucleo/board.h @@ -0,0 +1,269 @@ +/* board.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef BOARD_H +#define BOARD_H + +#include +#include +#include +#include +#include +#include +#include + +extern whal_Uart g_whalUart; +extern whal_Spi g_whalSpi; +extern whal_I2c g_whalI2c; +extern whal_Watchdog g_whalWatchdog; +#ifdef BOARD_DMA +extern whal_Dma g_whalDma1; +#endif + +extern whal_Timeout g_whalTimeout; +extern volatile uint32_t g_tick; + +enum { + LED_PIN, + UART_TX_PIN, + UART_RX_PIN, + SPI_SCK_PIN, + SPI_MISO_PIN, + SPI_MOSI_PIN, + SPI_CS_PIN, + I2C_SCL_PIN, + I2C_SDA_PIN, + PIN_COUNT, +}; + +#define BOARD_LED_PIN 0 +#define BOARD_FLASH_START_ADDR 0x08000000 +#define BOARD_FLASH_SIZE 0x400000 /* 4 MB — U5A5 dual-bank */ +#define BOARD_FLASH_TEST_ADDR 0x080FE000 +#define BOARD_FLASH_SECTOR_SZ 0x2000 /* 8 KB */ + +/* IWDG/WWDG dev initializers — singletons defined in stm32wb_iwdg.c / + * stm32wb_wwdg.c (stm32u5 alias points at stm32wb leaf). */ +#define WHAL_CFG_STM32U5_IWDG_DEV { \ + .base = WHAL_STM32U5A5_IWDG_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Iwdg_Cfg){ \ + .prescaler = WHAL_STM32U5_IWDG_PR_32, \ + .reload = 100, \ + .timeout = &g_whalTimeout, \ + }, \ +} + +#define WHAL_CFG_STM32U5_WWDG_DEV { \ + .base = WHAL_STM32U5A5_WWDG_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Wwdg_Cfg){ \ + .prescaler = WHAL_STM32U5_WWDG_TB_128, \ + .window = 0x7F, \ + .counter = 0x7F, \ + }, \ +} + +/* AES + mode dev initializers — singletons defined in stm32wb_aes.c + * (stm32u5 alias points at stm32wb leaf). Mutable GCM/CCM state buffers + * (g_stm32wbAesGcm/CcmDevState) are static in the driver TU. */ +#define WHAL_CFG_STM32U5_AES_DEV { \ + .base = WHAL_STM32U5A5_AES_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Aes_Cfg){ \ + .timeout = &g_whalTimeout, \ + }, \ +} + +#define WHAL_CFG_STM32U5_AES_ECB_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ +} + +#define WHAL_CFG_STM32U5_AES_CBC_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ +} + +#define WHAL_CFG_STM32U5_AES_CTR_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ +} + +#define WHAL_CFG_STM32U5_AES_GCM_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ + .state = &g_stm32wbAesGcmDevState, \ +} + +#define WHAL_CFG_STM32U5_AES_GMAC_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ +} + +#define WHAL_CFG_STM32U5_AES_CCM_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Aes_Dev, \ + .state = &g_stm32wbAesCcmDevState, \ +} + +/* RNG dev initializer — singleton defined in stm32wba_rng.c (alias). */ +#define WHAL_CFG_STM32U5_RNG_DEV { \ + .base = WHAL_STM32U5A5_RNG_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Rng_Cfg){ \ + .timeout = &g_whalTimeout, \ + }, \ +} + +/* Flash dev initializer — singleton defined in stm32u5_flash.c. */ +#define WHAL_CFG_STM32U5_FLASH_DEV { \ + .driver = WHAL_STM32U5A5_FLASH_DRIVER, \ + .base = WHAL_STM32U5A5_FLASH_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Flash_Cfg){ \ + .timeout = &g_whalTimeout, \ + .startAddr = 0x08000000, \ + .size = 0x400000, /* 4 MB total */ \ + .bankSize = 0x200000, /* 2 MB per bank, dual-bank */ \ + }, \ +} + +/* HASH + algorithm dev initializers — singletons defined in stm32wba_hash.c. */ +#define WHAL_CFG_STM32U5_HASH_DEV { \ + .base = WHAL_STM32U5A5_HASH_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Hash_Cfg){ \ + .timeout = &g_whalTimeout, \ + }, \ +} + +#define WHAL_CFG_STM32U5_HASH_SHA1_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +#define WHAL_CFG_STM32U5_HASH_SHA224_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +#define WHAL_CFG_STM32U5_HASH_SHA256_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +#define WHAL_CFG_STM32U5_HASH_HMAC_SHA1_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +#define WHAL_CFG_STM32U5_HASH_HMAC_SHA224_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +#define WHAL_CFG_STM32U5_HASH_HMAC_SHA256_DEV { \ + .crypto = (whal_Crypto *)&whal_Stm32u5_Hash_Dev, \ +} + +/* BOARD_*_DEV: how this board reaches each peripheral. */ +#define BOARD_GPIO_DEV WHAL_INTERNAL_DEV +#define BOARD_UART_DEV (&g_whalUart) +#define BOARD_SPI_DEV (&g_whalSpi) +#define BOARD_I2C_DEV (&g_whalI2c) +#define BOARD_FLASH_DEV ((whal_Flash *)&whal_Stm32u5_Flash_Dev) +#define BOARD_WATCHDOG_DEV (&g_whalWatchdog) +#define BOARD_RNG_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_ECB_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_CBC_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_CTR_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_GCM_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_GMAC_DEV WHAL_INTERNAL_DEV +#define BOARD_AES_CCM_DEV WHAL_INTERNAL_DEV +#define BOARD_SHA1_DEV WHAL_INTERNAL_DEV +#define BOARD_SHA224_DEV WHAL_INTERNAL_DEV +#define BOARD_SHA256_DEV WHAL_INTERNAL_DEV +#define BOARD_HMAC_SHA1_DEV WHAL_INTERNAL_DEV +#define BOARD_HMAC_SHA224_DEV WHAL_INTERNAL_DEV +#define BOARD_HMAC_SHA256_DEV WHAL_INTERNAL_DEV + +/* GPIO dev initializer — singleton defined in stm32wb_gpio.c (alias). */ +#define WHAL_CFG_STM32U5_GPIO_DEV { \ + .base = WHAL_STM32U5A5_GPIO_BASE, \ + .cfg = (void *)&(const whal_Stm32u5_Gpio_Cfg){ \ + .pinCfg = (const whal_Stm32u5_Gpio_PinCfg[PIN_COUNT]){ \ + /* LED: PC7 (NUCLEO-U5A5ZJ-Q LD1 green), output, push-pull, + * low speed, no pull */ \ + [LED_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_C, 7, WHAL_STM32U5_GPIO_MODE_OUT, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_LOW, \ + WHAL_STM32U5_GPIO_PULL_NONE, 0), \ + /* USART1 TX: PA9, AF7 (default Nucleo VCP TX) */ \ + [UART_TX_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_A, 9, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_UP, 7), \ + /* USART1 RX: PA10, AF7 (default Nucleo VCP RX) */ \ + [UART_RX_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_A, 10, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_UP, 7), \ + /* SPI1 SCK: PB3, AF5 */ \ + [SPI_SCK_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_B, 3, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_NONE, 5), \ + /* SPI1 MISO: PB4, AF5 */ \ + [SPI_MISO_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_B, 4, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_NONE, 5), \ + /* SPI1 MOSI: PB5, AF5 */ \ + [SPI_MOSI_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_B, 5, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_NONE, 5), \ + /* SPI CS: PA4, output, push-pull (avoids PA5 LED conflict) */ \ + [SPI_CS_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_A, 4, WHAL_STM32U5_GPIO_MODE_OUT, \ + WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_UP, 0), \ + /* I2C1 SCL: PB6, AF4, open-drain */ \ + [I2C_SCL_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_B, 6, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_UP, 4), \ + /* I2C1 SDA: PB7, AF4, open-drain */ \ + [I2C_SDA_PIN] = WHAL_STM32U5_GPIO_PIN( \ + WHAL_STM32U5_GPIO_PORT_B, 7, WHAL_STM32U5_GPIO_MODE_ALTFN, \ + WHAL_STM32U5_GPIO_OUTTYPE_OPENDRAIN, WHAL_STM32U5_GPIO_SPEED_FAST, \ + WHAL_STM32U5_GPIO_PULL_UP, 4), \ + }, \ + .pinCount = PIN_COUNT, \ + }, \ +} + +/* NVIC dev initializer — singleton defined in cortex_m33_nvic.c. */ +#define WHAL_CFG_NVIC_DEV { \ + .base = WHAL_CORTEX_M33_NVIC_BASE, \ + /* .driver: direct API mapping */ \ +} + +/* SysTick dev initializer — singleton defined in systick.c. */ +#define WHAL_CFG_SYSTICK_DEV { \ + .base = WHAL_CORTEX_M33_SYSTICK_BASE, \ + /* .driver: direct API mapping */ \ + .cfg = (void *)&(const whal_SysTick_Cfg){ \ + .cyclesPerTick = 160000000 / 1000, \ + .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK, \ + .tickInt = WHAL_SYSTICK_TICKINT_ENABLED, \ + }, \ +} + +whal_Error Board_Init(void); +whal_Error Board_Deinit(void); +void Board_WaitMs(size_t ms); + +#endif /* BOARD_H */ diff --git a/boards/stm32u5a5zj_nucleo/board.mk b/boards/stm32u5a5zj_nucleo/board.mk new file mode 100644 index 0000000..6b49b83 --- /dev/null +++ b/boards/stm32u5a5zj_nucleo/board.mk @@ -0,0 +1,88 @@ +# board.mk +# +# Copyright (C) 2026 wolfSSL Inc. +# +# This file is part of wolfHAL. +# +# wolfHAL is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# wolfHAL is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA +# + +_BOARD_DIR := $(patsubst %/,%,$(dir $(lastword $(MAKEFILE_LIST)))) + +PLATFORM = stm32u5 +TESTS ?= gpio flash timer rng aes_ecb aes_cbc aes_ctr aes_gcm aes_gmac aes_ccm sha1 sha224 sha256 hmac_sha1 hmac_sha224 hmac_sha256 uart spi i2c + +GCC = $(GCC_PATH)arm-none-eabi-gcc +LD = $(GCC_PATH)arm-none-eabi-ld +OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy + +CFLAGS += -Wall -Werror $(INCLUDE) -g3 -Os -ffunction-sections -fdata-sections \ + -ffreestanding -nostdlib -mcpu=cortex-m33 -mthumb \ + -DPLATFORM_STM32U5 -MMD -MP \ + -DWHAL_CFG_STM32U5_AES_ECB_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_AES_CBC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_AES_CTR_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_AES_GCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_AES_GMAC_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_AES_CCM_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_SHA256_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_HMAC_SHA1_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_HMAC_SHA224_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_HASH_HMAC_SHA256_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_GPIO_DIRECT_API_MAPPING \ + -DWHAL_CFG_STM32U5_RNG_DIRECT_API_MAPPING \ + $(if $(DMA),-DBOARD_DMA) \ + $(if $(filter iwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_IWDG) \ + $(if $(filter wwdg,$(WATCHDOG)),-DBOARD_WATCHDOG_WWDG) \ + -DWHAL_CFG_SYSTICK_TIMER_DIRECT_API_MAPPING \ + -DWHAL_CFG_NVIC_IRQ_DIRECT_API_MAPPING +LDFLAGS = --omagic -static --gc-sections + +LINKER_SCRIPT ?= $(_BOARD_DIR)/linker.ld + +INCLUDE += -I$(_BOARD_DIR) -I$(WHAL_DIR)/boards/peripheral + +BOARD_SOURCE = $(_BOARD_DIR)/ivt.c +BOARD_SOURCE += $(_BOARD_DIR)/board.c +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/clock.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/uart.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/flash.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/spi.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/i2c.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/sensor.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/watchdog.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/crypto.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/block.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/dma.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/irq/cortex_m4_nvic.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/stm32u5_*.c) +BOARD_SOURCE += $(wildcard $(WHAL_DIR)/src/*/systick.c) + +# Peripheral devices +include $(WHAL_DIR)/boards/peripheral/board.mk + +# Flash via openocd: make flash BOARD= IMAGE= +OPENOCD ?= /opt/openocd/bin/openocd +OPENOCD_INTERFACE ?= interface/stlink.cfg +OPENOCD_TARGET ?= target/stm32u5x.cfg + +.PHONY: flash +flash: + @test -n "$(IMAGE)" || { echo "IMAGE= required" >&2; exit 1; } + $(OPENOCD) -f $(OPENOCD_INTERFACE) -f $(OPENOCD_TARGET) \ + -c "program $(IMAGE) verify reset exit" diff --git a/boards/stm32u5a5zj_nucleo/ivt.c b/boards/stm32u5a5zj_nucleo/ivt.c new file mode 100644 index 0000000..b529e76 --- /dev/null +++ b/boards/stm32u5a5zj_nucleo/ivt.c @@ -0,0 +1,364 @@ +/* ivt.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include + +extern uint32_t _estack[]; +extern uint32_t _sidata[]; +extern uint32_t _sdata[]; +extern uint32_t _edata[]; +extern uint32_t _sbss[]; +extern uint32_t _ebss[]; + +extern void main(); + +void __attribute__((naked,noreturn)) Default_Handler() +{ + while(1); +} + +void Reset_Handler() __attribute__((weak)); +void NMI_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void HardFault_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MemManage_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void BusFault_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void UsageFault_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SecureFault_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SVC_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void DebugMon_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void PendSV_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SysTick_Handler() __attribute__((weak, noreturn, alias("Default_Handler"))); + +/* STM32U5A5 IRQ handlers (positions 0-124 per RM0456 NVIC mapping) */ +void WWDG_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void PVD_PVM_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RTC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RTC_S_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TAMP_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RAMCFG_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FLASH_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FLASH_S_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GTZC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RCC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RCC_S_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI0_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI5_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI6_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI7_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI8_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI9_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI10_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI11_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI12_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI13_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI14_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void EXTI15_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void IWDG_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SAES_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel0_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel5_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel6_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel7_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void ADC1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void DAC1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FDCAN1_IT0_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FDCAN1_IT1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM1_BRK_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM1_UP_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM1_TRG_COM_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM1_CC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM5_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM6_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM7_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM8_BRK_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM8_UP_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM8_TRG_COM_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM8_CC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C1_EV_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C1_ER_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C2_EV_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C2_ER_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SPI1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SPI2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void USART1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void USART2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void USART3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void UART4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void UART5_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPUART1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPTIM1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPTIM2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM15_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM16_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TIM17_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void COMP_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void OTG_FS_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void CRS_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FMC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void OCTOSPI1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void PWR_S3WU_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SDMMC1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SDMMC2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel8_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel9_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel10_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel11_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel12_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel13_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel14_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void GPDMA1_Channel15_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C3_EV_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C3_ER_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SAI1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SAI2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void TSC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void RNG_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FPU_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void HASH_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void PKA_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPTIM3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void SPI3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C4_ER_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void I2C4_EV_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT0_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void UCPD1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void ICACHE_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPTIM4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void DCACHE1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void ADF1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void ADC4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPDMA1_Channel0_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPDMA1_Channel1_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPDMA1_Channel2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void LPDMA1_Channel3_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void DMA2D_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void DCMI_PSSI_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void OCTOSPI2_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT4_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void MDF1_FLT5_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void CORDIC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); +void FMAC_IRQHandler() __attribute__((weak, noreturn, alias("Default_Handler"))); + +#define RESERVED Default_Handler + +/* + * Cortex-M33 vector table for STM32U5A5xx. + * Positions per RM0456 NVIC interrupt mapping (124 external interrupts). + */ +void (* const interrupt_vector_table[])() __attribute__((section(".isr_vector"))) = { + (void (*)())_estack, /* Initial stack pointer */ + Reset_Handler, /* Reset */ + NMI_Handler, /* NMI */ + HardFault_Handler, /* Hard fault */ + MemManage_Handler, /* Memory management fault */ + BusFault_Handler, /* Bus fault */ + UsageFault_Handler, /* Usage fault */ + SecureFault_Handler, /* Secure fault (Cortex-M33) */ + RESERVED, /* Reserved */ + RESERVED, /* Reserved */ + RESERVED, /* Reserved */ + SVC_Handler, /* SVCall */ + DebugMon_Handler, /* Debug monitor */ + RESERVED, /* Reserved */ + PendSV_Handler, /* PendSV */ + SysTick_Handler, /* SysTick */ + /* External interrupts (position 0+) */ + WWDG_IRQHandler, /* 0: Window watchdog */ + PVD_PVM_IRQHandler, /* 1: PVD/PVM */ + RTC_IRQHandler, /* 2: RTC non-secure */ + RTC_S_IRQHandler, /* 3: RTC secure */ + TAMP_IRQHandler, /* 4: Tamper non-secure */ + RAMCFG_IRQHandler, /* 5: RAMCFG */ + FLASH_IRQHandler, /* 6: Flash non-secure */ + FLASH_S_IRQHandler, /* 7: Flash secure */ + GTZC_IRQHandler, /* 8: GTZC TZIC */ + RCC_IRQHandler, /* 9: RCC non-secure */ + RCC_S_IRQHandler, /* 10: RCC secure */ + EXTI0_IRQHandler, /* 11: EXTI line 0 */ + EXTI1_IRQHandler, /* 12: EXTI line 1 */ + EXTI2_IRQHandler, /* 13: EXTI line 2 */ + EXTI3_IRQHandler, /* 14: EXTI line 3 */ + EXTI4_IRQHandler, /* 15: EXTI line 4 */ + EXTI5_IRQHandler, /* 16: EXTI line 5 */ + EXTI6_IRQHandler, /* 17: EXTI line 6 */ + EXTI7_IRQHandler, /* 18: EXTI line 7 */ + EXTI8_IRQHandler, /* 19: EXTI line 8 */ + EXTI9_IRQHandler, /* 20: EXTI line 9 */ + EXTI10_IRQHandler, /* 21: EXTI line 10 */ + EXTI11_IRQHandler, /* 22: EXTI line 11 */ + EXTI12_IRQHandler, /* 23: EXTI line 12 */ + EXTI13_IRQHandler, /* 24: EXTI line 13 */ + EXTI14_IRQHandler, /* 25: EXTI line 14 */ + EXTI15_IRQHandler, /* 26: EXTI line 15 */ + IWDG_IRQHandler, /* 27: IWDG */ + SAES_IRQHandler, /* 28: Secure AES */ + GPDMA1_Channel0_IRQHandler, /* 29: GPDMA1 channel 0 */ + GPDMA1_Channel1_IRQHandler, /* 30: GPDMA1 channel 1 */ + GPDMA1_Channel2_IRQHandler, /* 31: GPDMA1 channel 2 */ + GPDMA1_Channel3_IRQHandler, /* 32: GPDMA1 channel 3 */ + GPDMA1_Channel4_IRQHandler, /* 33: GPDMA1 channel 4 */ + GPDMA1_Channel5_IRQHandler, /* 34: GPDMA1 channel 5 */ + GPDMA1_Channel6_IRQHandler, /* 35: GPDMA1 channel 6 */ + GPDMA1_Channel7_IRQHandler, /* 36: GPDMA1 channel 7 */ + ADC1_IRQHandler, /* 37: ADC1 */ + DAC1_IRQHandler, /* 38: DAC1 */ + FDCAN1_IT0_IRQHandler, /* 39: FDCAN1 IT0 */ + FDCAN1_IT1_IRQHandler, /* 40: FDCAN1 IT1 */ + TIM1_BRK_IRQHandler, /* 41: TIM1 break */ + TIM1_UP_IRQHandler, /* 42: TIM1 update */ + TIM1_TRG_COM_IRQHandler, /* 43: TIM1 trigger/commutation */ + TIM1_CC_IRQHandler, /* 44: TIM1 capture compare */ + TIM2_IRQHandler, /* 45: TIM2 */ + TIM3_IRQHandler, /* 46: TIM3 */ + TIM4_IRQHandler, /* 47: TIM4 */ + TIM5_IRQHandler, /* 48: TIM5 */ + TIM6_IRQHandler, /* 49: TIM6 */ + TIM7_IRQHandler, /* 50: TIM7 */ + TIM8_BRK_IRQHandler, /* 51: TIM8 break */ + TIM8_UP_IRQHandler, /* 52: TIM8 update */ + TIM8_TRG_COM_IRQHandler, /* 53: TIM8 trigger/commutation */ + TIM8_CC_IRQHandler, /* 54: TIM8 capture compare */ + I2C1_EV_IRQHandler, /* 55: I2C1 event */ + I2C1_ER_IRQHandler, /* 56: I2C1 error */ + I2C2_EV_IRQHandler, /* 57: I2C2 event */ + I2C2_ER_IRQHandler, /* 58: I2C2 error */ + SPI1_IRQHandler, /* 59: SPI1 */ + SPI2_IRQHandler, /* 60: SPI2 */ + USART1_IRQHandler, /* 61: USART1 */ + USART2_IRQHandler, /* 62: USART2 */ + USART3_IRQHandler, /* 63: USART3 */ + UART4_IRQHandler, /* 64: UART4 */ + UART5_IRQHandler, /* 65: UART5 */ + LPUART1_IRQHandler, /* 66: LPUART1 */ + LPTIM1_IRQHandler, /* 67: LPTIM1 */ + LPTIM2_IRQHandler, /* 68: LPTIM2 */ + TIM15_IRQHandler, /* 69: TIM15 */ + TIM16_IRQHandler, /* 70: TIM16 */ + TIM17_IRQHandler, /* 71: TIM17 */ + COMP_IRQHandler, /* 72: COMP */ + OTG_FS_IRQHandler, /* 73: OTG_FS */ + CRS_IRQHandler, /* 74: CRS */ + FMC_IRQHandler, /* 75: FMC */ + OCTOSPI1_IRQHandler, /* 76: OCTOSPI1 */ + PWR_S3WU_IRQHandler, /* 77: PWR S3WU */ + SDMMC1_IRQHandler, /* 78: SDMMC1 */ + SDMMC2_IRQHandler, /* 79: SDMMC2 */ + GPDMA1_Channel8_IRQHandler, /* 80: GPDMA1 channel 8 */ + GPDMA1_Channel9_IRQHandler, /* 81: GPDMA1 channel 9 */ + GPDMA1_Channel10_IRQHandler, /* 82: GPDMA1 channel 10 */ + GPDMA1_Channel11_IRQHandler, /* 83: GPDMA1 channel 11 */ + GPDMA1_Channel12_IRQHandler, /* 84: GPDMA1 channel 12 */ + GPDMA1_Channel13_IRQHandler, /* 85: GPDMA1 channel 13 */ + GPDMA1_Channel14_IRQHandler, /* 86: GPDMA1 channel 14 */ + GPDMA1_Channel15_IRQHandler, /* 87: GPDMA1 channel 15 */ + I2C3_EV_IRQHandler, /* 88: I2C3 event */ + I2C3_ER_IRQHandler, /* 89: I2C3 error */ + SAI1_IRQHandler, /* 90: SAI1 */ + SAI2_IRQHandler, /* 91: SAI2 */ + TSC_IRQHandler, /* 92: TSC */ + RESERVED, /* 93: reserved (AES not present on nonsecure side) */ + RNG_IRQHandler, /* 94: RNG */ + FPU_IRQHandler, /* 95: FPU */ + HASH_IRQHandler, /* 96: HASH */ + PKA_IRQHandler, /* 97: PKA */ + LPTIM3_IRQHandler, /* 98: LPTIM3 */ + SPI3_IRQHandler, /* 99: SPI3 */ + I2C4_ER_IRQHandler, /* 100: I2C4 error */ + I2C4_EV_IRQHandler, /* 101: I2C4 event */ + MDF1_FLT0_IRQHandler, /* 102: MDF1 filter 0 */ + MDF1_FLT1_IRQHandler, /* 103: MDF1 filter 1 */ + MDF1_FLT2_IRQHandler, /* 104: MDF1 filter 2 */ + MDF1_FLT3_IRQHandler, /* 105: MDF1 filter 3 */ + UCPD1_IRQHandler, /* 106: UCPD1 */ + ICACHE_IRQHandler, /* 107: ICACHE */ + LPTIM4_IRQHandler, /* 108: LPTIM4 */ + DCACHE1_IRQHandler, /* 109: DCACHE1 */ + ADF1_IRQHandler, /* 110: ADF1 */ + ADC4_IRQHandler, /* 111: ADC4 */ + LPDMA1_Channel0_IRQHandler, /* 112: LPDMA1 channel 0 */ + LPDMA1_Channel1_IRQHandler, /* 113: LPDMA1 channel 1 */ + LPDMA1_Channel2_IRQHandler, /* 114: LPDMA1 channel 2 */ + LPDMA1_Channel3_IRQHandler, /* 115: LPDMA1 channel 3 */ + DMA2D_IRQHandler, /* 116: DMA2D */ + DCMI_PSSI_IRQHandler, /* 117: DCMI/PSSI */ + OCTOSPI2_IRQHandler, /* 118: OCTOSPI2 */ + MDF1_FLT4_IRQHandler, /* 119: MDF1 filter 4 */ + MDF1_FLT5_IRQHandler, /* 120: MDF1 filter 5 */ + CORDIC_IRQHandler, /* 121: CORDIC */ + FMAC_IRQHandler, /* 122: FMAC */ +}; + +void *memcpy(void *dest, const void *src, size_t n) +{ + unsigned char *d = dest; + const unsigned char *s = src; + + for (size_t i = 0; i < n; i++) + d[i] = s[i]; + + return dest; +} + +void *memset(void *s, int c, size_t n) +{ + unsigned char *p = s; + unsigned char v = (unsigned char)c; + + for (size_t i = 0; i < n; i++) + p[i] = v; + + return s; +} + +void __attribute__((naked)) Reset_Handler() +{ + __asm__("ldr r0, =_estack\n\t" + "mov sp, r0"); + + /* Copy data section from flash to RAM */ + uint32_t data_section_size = _edata - _sdata; + memcpy(_sdata, _sidata, data_section_size*4); + + /* Zero out bss */ + uint32_t bss_section_size = _ebss - _sbss; + memset(_sbss, 0, bss_section_size*4); + + /* Set Interrupt Vector Table Offset */ + uint32_t *vtor = (uint32_t *)0xE000ED08; + *vtor = (uint32_t)interrupt_vector_table; + + main(); +} diff --git a/boards/stm32u5a5zj_nucleo/linker.ld b/boards/stm32u5a5zj_nucleo/linker.ld new file mode 100644 index 0000000..ee2add8 --- /dev/null +++ b/boards/stm32u5a5zj_nucleo/linker.ld @@ -0,0 +1,149 @@ +/* linker.ld + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +/* + * Linker script for STM32U5A5ZJ (modelled on NUCLEO-U5A5ZJ-Q) + * + * Flash: 4 MB at 0x08000000 (dual-bank — 2x 2 MB) + * SRAM1: 768 KB at 0x20000000 + * SRAM2: 64 KB at 0x200C0000 (contiguous with SRAM1) + */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x200D0000; /* end of SRAM1+SRAM2 (832 KB) */ +/* Generate a link error if the stack doesn't fit into RAM */ +_Min_Stack_Size = 0x500; + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 4096K +RAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x000D0000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM1 AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM1 + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM1 +} diff --git a/boards/stm32wba55cg_nucleo/board.h b/boards/stm32wba55cg_nucleo/board.h index 63c7231..618849d 100644 --- a/boards/stm32wba55cg_nucleo/board.h +++ b/boards/stm32wba55cg_nucleo/board.h @@ -63,7 +63,7 @@ enum { /* IWDG/WWDG dev initializers — singletons defined in stm32wb_iwdg.c / * stm32wb_wwdg.c (stm32wba is an include alias). */ -#define WHAL_CFG_STM32WB_IWDG_DEV { \ +#define WHAL_CFG_STM32WBA_IWDG_DEV { \ .base = WHAL_STM32WBA55_IWDG_BASE, \ .cfg = (void *)&(const whal_Stm32wba_Iwdg_Cfg){ \ .prescaler = WHAL_STM32WBA_IWDG_PR_32, \ @@ -72,7 +72,7 @@ enum { }, \ } -#define WHAL_CFG_STM32WB_WWDG_DEV { \ +#define WHAL_CFG_STM32WBA_WWDG_DEV { \ .base = WHAL_STM32WBA55_WWDG_BASE, \ .cfg = (void *)&(const whal_Stm32wba_Wwdg_Cfg){ \ .prescaler = WHAL_STM32WBA_WWDG_TB_128, \ @@ -84,35 +84,35 @@ enum { /* AES + mode dev initializers — singletons defined in stm32wb_aes.c * (stm32wba is an include alias). Mutable GCM/CCM state buffers * (g_stm32wbAesGcm/CcmDevState) are static in the driver TU. */ -#define WHAL_CFG_STM32WB_AES_DEV { \ +#define WHAL_CFG_STM32WBA_AES_DEV { \ .base = WHAL_STM32WBA55_AES_BASE, \ .cfg = (void *)&(const whal_Stm32wba_Aes_Cfg){ \ .timeout = &g_whalTimeout, \ }, \ } -#define WHAL_CFG_STM32WB_AES_ECB_DEV { \ +#define WHAL_CFG_STM32WBA_AES_ECB_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ } -#define WHAL_CFG_STM32WB_AES_CBC_DEV { \ +#define WHAL_CFG_STM32WBA_AES_CBC_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ } -#define WHAL_CFG_STM32WB_AES_CTR_DEV { \ +#define WHAL_CFG_STM32WBA_AES_CTR_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ } -#define WHAL_CFG_STM32WB_AES_GCM_DEV { \ +#define WHAL_CFG_STM32WBA_AES_GCM_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ .state = &g_stm32wbAesGcmDevState, \ } -#define WHAL_CFG_STM32WB_AES_GMAC_DEV { \ +#define WHAL_CFG_STM32WBA_AES_GMAC_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ } -#define WHAL_CFG_STM32WB_AES_CCM_DEV { \ +#define WHAL_CFG_STM32WBA_AES_CCM_DEV { \ .crypto = (whal_Crypto *)&whal_Stm32wb_Aes_Dev, \ .state = &g_stm32wbAesCcmDevState, \ } @@ -190,7 +190,7 @@ enum { #define BOARD_HMAC_SHA256_DEV WHAL_INTERNAL_DEV /* GPIO dev initializer — singleton defined in driver TU. */ -#define WHAL_CFG_STM32WB_GPIO_DEV { \ +#define WHAL_CFG_STM32WBA_GPIO_DEV { \ .base = WHAL_STM32WBA55_GPIO_BASE, \ .driver = WHAL_STM32WBA55_GPIO_DRIVER, \ .cfg = (void *)&(const whal_Stm32wba_Gpio_Cfg){ \ diff --git a/src/crypto/stm32n6_hash.c b/src/crypto/stm32n6_hash.c index 143be53..991b8ef 100644 --- a/src/crypto/stm32n6_hash.c +++ b/src/crypto/stm32n6_hash.c @@ -19,4 +19,25 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_HASH_INIT_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_SHA1_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_SHA224_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_SHA256_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_HMAC_SHA1_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_HMAC_SHA224_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING +#endif #include "stm32wba_hash.c" diff --git a/src/crypto/stm32u5_aes.c b/src/crypto/stm32u5_aes.c new file mode 100644 index 0000000..07f5f36 --- /dev/null +++ b/src/crypto/stm32u5_aes.c @@ -0,0 +1,22 @@ +#ifdef WHAL_CFG_STM32U5_AES_INIT_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_INIT_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_ECB_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_ECB_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_CBC_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CBC_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_CTR_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CTR_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_GCM_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_GCM_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_GMAC_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_GMAC_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_AES_CCM_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_AES_CCM_DIRECT_API_MAPPING +#endif +#include "stm32wb_aes.c" diff --git a/src/crypto/stm32u5_hash.c b/src/crypto/stm32u5_hash.c new file mode 100644 index 0000000..2ec4a0f --- /dev/null +++ b/src/crypto/stm32u5_hash.c @@ -0,0 +1,22 @@ +#ifdef WHAL_CFG_STM32U5_HASH_INIT_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_SHA1_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_SHA224_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_SHA256_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_HMAC_SHA1_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_HMAC_SHA224_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_HASH_HMAC_SHA256_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING +#endif +#include "stm32wba_hash.c" diff --git a/src/crypto/stm32wba_hash.c b/src/crypto/stm32wba_hash.c index 815d366..920f4f7 100644 --- a/src/crypto/stm32wba_hash.c +++ b/src/crypto/stm32wba_hash.c @@ -88,6 +88,14 @@ static whal_Stm32wba_HmacSha1_State g_hmacSha1State; static whal_Stm32wba_HmacSha224_State g_hmacSha224State; static whal_Stm32wba_HmacSha256_State g_hmacSha256State; +/* Hash peripheral is single-instance, so one shared 0-3 byte staging + * buffer is enough — only one streaming session can be live at a time. + * Process accumulates leftover bytes here until the next call brings the + * count to 4 (push as a full word) or Finalize drains them as the + * genuine last partial word. */ +static uint8_t g_streamBuf[4]; +static size_t g_streamBufBytes; + static uint32_t AlgoBits(size_t algo) { return whal_SetBits(HASH_CR_ALGO_Msk, HASH_CR_ALGO_Pos, algo); @@ -98,7 +106,43 @@ static whal_Error WaitForReady(size_t base, whal_Timeout *timeout) return whal_Reg_ReadPoll(base, HASH_SR_REG, HASH_SR_BUSY_Msk, 0, timeout); } -static void WriteData(size_t base, const uint8_t *in, size_t inSz) +/* Reset the stream staging buffer; called from each Start. */ +static void StreamReset(void) +{ + g_streamBufBytes = 0; +} + +/* Accumulate Process input. Tops up the staging buffer to a full word if + * it had leftovers, pushes full 32-bit DIN writes, and stashes the + * trailing 0-3 bytes back into the staging buffer for the next call. */ +static void StreamWrite(size_t base, const uint8_t *in, size_t inSz) +{ + if (g_streamBufBytes > 0) { + while (g_streamBufBytes < 4 && inSz > 0) { + g_streamBuf[g_streamBufBytes++] = *in++; + inSz--; + } + if (g_streamBufBytes == 4) { + whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(g_streamBuf)); + g_streamBufBytes = 0; + } + } + + while (inSz >= 4) { + whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); + in += 4; + inSz -= 4; + } + + while (inSz > 0) { + g_streamBuf[g_streamBufBytes++] = *in++; + inSz--; + } +} + +/* Push inSz bytes immediately before issuing DCAL: full words first, then + * if any trailing bytes remain, set NBLW and push one partial word. */ +static void WriteTail(size_t base, const uint8_t *in, size_t inSz) { while (inSz >= 4) { whal_Reg_Write(base, HASH_DIN_REG, whal_LoadBe32(in)); @@ -114,6 +158,14 @@ static void WriteData(size_t base, const uint8_t *in, size_t inSz) } } +/* Drain any buffered 0-3 trailing bytes as the final partial word right + * before DCAL; sets NBLW correctly via WriteTail. */ +static void StreamDrain(size_t base) +{ + WriteTail(base, g_streamBuf, g_streamBufBytes); + g_streamBufBytes = 0; +} + static void ReadDigest(size_t base, uint8_t *digest, size_t digestSz) { size_t words = digestSz / 4; @@ -128,54 +180,47 @@ static void ReadDigest(size_t base, uint8_t *digest, size_t digestSz) /* ---- Direct API mapping ---- */ -#if defined(WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_INIT_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_INIT_DIRECT_API_MAPPING #define whal_Stm32wba_Hash_Init whal_Crypto_Init #define whal_Stm32wba_Hash_Deinit whal_Crypto_Deinit #endif -#if defined(WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_SHA1_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_SHA1_DIRECT_API_MAPPING #define whal_Stm32wba_Sha1_Oneshot whal_Sha1_Oneshot #define whal_Stm32wba_Sha1_Start whal_Sha1_Start #define whal_Stm32wba_Sha1_Process whal_Sha1_Process #define whal_Stm32wba_Sha1_Finalize whal_Sha1_Finalize #endif -#if defined(WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_SHA224_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_SHA224_DIRECT_API_MAPPING #define whal_Stm32wba_Sha224_Oneshot whal_Sha224_Oneshot #define whal_Stm32wba_Sha224_Start whal_Sha224_Start #define whal_Stm32wba_Sha224_Process whal_Sha224_Process #define whal_Stm32wba_Sha224_Finalize whal_Sha224_Finalize #endif -#if defined(WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_SHA256_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_SHA256_DIRECT_API_MAPPING #define whal_Stm32wba_Sha256_Oneshot whal_Sha256_Oneshot #define whal_Stm32wba_Sha256_Start whal_Sha256_Start #define whal_Stm32wba_Sha256_Process whal_Sha256_Process #define whal_Stm32wba_Sha256_Finalize whal_Sha256_Finalize #endif -#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA1_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DIRECT_API_MAPPING #define whal_Stm32wba_HmacSha1_Oneshot whal_HmacSha1_Oneshot #define whal_Stm32wba_HmacSha1_Start whal_HmacSha1_Start #define whal_Stm32wba_HmacSha1_Process whal_HmacSha1_Process #define whal_Stm32wba_HmacSha1_Finalize whal_HmacSha1_Finalize #endif -#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA224_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DIRECT_API_MAPPING #define whal_Stm32wba_HmacSha224_Oneshot whal_HmacSha224_Oneshot #define whal_Stm32wba_HmacSha224_Start whal_HmacSha224_Start #define whal_Stm32wba_HmacSha224_Process whal_HmacSha224_Process #define whal_Stm32wba_HmacSha224_Finalize whal_HmacSha224_Finalize #endif -#if defined(WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_HASH_HMAC_SHA256_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DIRECT_API_MAPPING #define whal_Stm32wba_HmacSha256_Oneshot whal_HmacSha256_Oneshot #define whal_Stm32wba_HmacSha256_Start whal_HmacSha256_Start #define whal_Stm32wba_HmacSha256_Process whal_HmacSha256_Process @@ -228,7 +273,7 @@ whal_Error whal_Stm32wba_Sha1_Oneshot(whal_Sha1 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -254,6 +299,7 @@ whal_Error whal_Stm32wba_Sha1_Start(whal_Sha1 *dev) HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, AlgoBits(HASH_ALGO_SHA1) | HASH_CR_INIT_Msk); + StreamReset(); return WHAL_SUCCESS; } @@ -261,11 +307,11 @@ whal_Error whal_Stm32wba_Sha1_Process(whal_Sha1 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -281,6 +327,8 @@ whal_Error whal_Stm32wba_Sha1_Finalize(whal_Sha1 *dev, if (!digest || digestSz != 20) return WHAL_EINVAL; + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -325,7 +373,7 @@ whal_Error whal_Stm32wba_Sha224_Oneshot(whal_Sha224 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -351,6 +399,7 @@ whal_Error whal_Stm32wba_Sha224_Start(whal_Sha224 *dev) HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, AlgoBits(HASH_ALGO_SHA224) | HASH_CR_INIT_Msk); + StreamReset(); return WHAL_SUCCESS; } @@ -358,11 +407,11 @@ whal_Error whal_Stm32wba_Sha224_Process(whal_Sha224 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -378,6 +427,8 @@ whal_Error whal_Stm32wba_Sha224_Finalize(whal_Sha224 *dev, if (!digest || digestSz != 28) return WHAL_EINVAL; + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -422,7 +473,7 @@ whal_Error whal_Stm32wba_Sha256_Oneshot(whal_Sha256 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -448,6 +499,7 @@ whal_Error whal_Stm32wba_Sha256_Start(whal_Sha256 *dev) HASH_CR_MODE_Msk | HASH_CR_LKEY_Msk | HASH_CR_INIT_Msk, AlgoBits(HASH_ALGO_SHA256) | HASH_CR_INIT_Msk); + StreamReset(); return WHAL_SUCCESS; } @@ -455,11 +507,11 @@ whal_Error whal_Stm32wba_Sha256_Process(whal_Sha256 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -475,6 +527,8 @@ whal_Error whal_Stm32wba_Sha256_Finalize(whal_Sha256 *dev, if (!digest || digestSz != 32) return WHAL_EINVAL; + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -525,7 +579,7 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -538,7 +592,7 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -550,7 +604,7 @@ whal_Error whal_Stm32wba_HmacSha1_Oneshot(whal_HmacSha1 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -590,7 +644,7 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -603,6 +657,7 @@ whal_Error whal_Stm32wba_HmacSha1_Start(whal_HmacSha1 *dev, g_hmacSha1State.key = key; g_hmacSha1State.keySz = keySz; + StreamReset(); return WHAL_SUCCESS; } @@ -610,11 +665,11 @@ whal_Error whal_Stm32wba_HmacSha1_Process(whal_HmacSha1 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -630,7 +685,9 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, if (!digest || digestSz != 20) return WHAL_EINVAL; - /* Message done */ + /* Drain any buffered tail bytes, then DCAL to close message phase. */ + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -640,7 +697,7 @@ whal_Error whal_Stm32wba_HmacSha1_Finalize(whal_HmacSha1 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)g_hmacSha1State.key, g_hmacSha1State.keySz); + WriteTail(base, (const uint8_t *)g_hmacSha1State.key, g_hmacSha1State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -692,7 +749,7 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -705,7 +762,7 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -717,7 +774,7 @@ whal_Error whal_Stm32wba_HmacSha224_Oneshot(whal_HmacSha224 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -757,7 +814,7 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -770,6 +827,7 @@ whal_Error whal_Stm32wba_HmacSha224_Start(whal_HmacSha224 *dev, g_hmacSha224State.key = key; g_hmacSha224State.keySz = keySz; + StreamReset(); return WHAL_SUCCESS; } @@ -777,11 +835,11 @@ whal_Error whal_Stm32wba_HmacSha224_Process(whal_HmacSha224 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -797,7 +855,9 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, if (!digest || digestSz != 28) return WHAL_EINVAL; - /* Message done */ + /* Drain any buffered tail bytes, then DCAL to close message phase. */ + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -807,7 +867,7 @@ whal_Error whal_Stm32wba_HmacSha224_Finalize(whal_HmacSha224 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)g_hmacSha224State.key, g_hmacSha224State.keySz); + WriteTail(base, (const uint8_t *)g_hmacSha224State.key, g_hmacSha224State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -859,7 +919,7 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -872,7 +932,7 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, if (inSz > 0) { if (!in) return WHAL_EINVAL; - WriteData(base, (const uint8_t *)in, inSz); + WriteTail(base, (const uint8_t *)in, inSz); } whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, @@ -884,7 +944,7 @@ whal_Error whal_Stm32wba_HmacSha256_Oneshot(whal_HmacSha256 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -924,7 +984,7 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, HASH_CR_INIT_Msk); /* Inner key */ - WriteData(base, (const uint8_t *)key, keySz); + WriteTail(base, (const uint8_t *)key, keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -937,6 +997,7 @@ whal_Error whal_Stm32wba_HmacSha256_Start(whal_HmacSha256 *dev, g_hmacSha256State.key = key; g_hmacSha256State.keySz = keySz; + StreamReset(); return WHAL_SUCCESS; } @@ -944,11 +1005,11 @@ whal_Error whal_Stm32wba_HmacSha256_Process(whal_HmacSha256 *dev, const void *in, size_t inSz) { (void)dev; - if (inSz > 0) { - if (!in) - return WHAL_EINVAL; - WriteData(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); - } + if (inSz == 0) + return WHAL_SUCCESS; + if (!in) + return WHAL_EINVAL; + StreamWrite(whal_Stm32wba_Hash_Dev.base, (const uint8_t *)in, inSz); return WHAL_SUCCESS; } @@ -964,7 +1025,9 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, if (!digest || digestSz != 32) return WHAL_EINVAL; - /* Message done */ + /* Drain any buffered tail bytes, then DCAL to close message phase. */ + StreamDrain(base); + whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); @@ -974,7 +1037,7 @@ whal_Error whal_Stm32wba_HmacSha256_Finalize(whal_HmacSha256 *dev, /* Outer key */ whal_Reg_Update(base, HASH_STR_REG, HASH_STR_NBLW_Msk, 0); - WriteData(base, (const uint8_t *)g_hmacSha256State.key, g_hmacSha256State.keySz); + WriteTail(base, (const uint8_t *)g_hmacSha256State.key, g_hmacSha256State.keySz); whal_Reg_Update(base, HASH_STR_REG, HASH_STR_DCAL_Msk, HASH_STR_DCAL_Msk); diff --git a/src/dma/stm32n6_gpdma.c b/src/dma/stm32n6_gpdma.c index 43528d0..5aa112a 100644 --- a/src/dma/stm32n6_gpdma.c +++ b/src/dma/stm32n6_gpdma.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_GPDMA_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE +#define WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE +#endif #include "stm32wba_gpdma.c" diff --git a/src/dma/stm32u5_gpdma.c b/src/dma/stm32u5_gpdma.c new file mode 100644 index 0000000..ec3ac64 --- /dev/null +++ b/src/dma/stm32u5_gpdma.c @@ -0,0 +1,7 @@ +#ifdef WHAL_CFG_STM32U5_GPDMA_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_GPDMA_SINGLE_INSTANCE +#define WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE +#endif +#include "stm32wba_gpdma.c" diff --git a/src/dma/stm32wba_gpdma.c b/src/dma/stm32wba_gpdma.c index 00508bd..f70151e 100644 --- a/src/dma/stm32wba_gpdma.c +++ b/src/dma/stm32wba_gpdma.c @@ -21,8 +21,7 @@ #include #include -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32wba_Gpdma_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -129,8 +128,7 @@ #define GPDMA_CxTR2_DREQ_Pos 10 /* Direction: 0=src periph, 1=dst periph */ #define GPDMA_CxTR2_DREQ_Msk (1UL << GPDMA_CxTR2_DREQ_Pos) -#if defined(WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_GPDMA_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING #define whal_Stm32wba_Gpdma_Init whal_Dma_Init #define whal_Stm32wba_Gpdma_Deinit whal_Dma_Deinit #define whal_Stm32wba_Gpdma_Configure whal_Dma_Configure @@ -138,15 +136,13 @@ #define whal_Stm32wba_Gpdma_Stop whal_Dma_Stop #endif -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Dma whal_Stm32wba_Gpdma_Dev = WHAL_CFG_STM32WBA_GPDMA_DEV; #endif whal_Error whal_Stm32wba_Gpdma_Init(whal_Dma *dmaDev) { -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE (void)dmaDev; #else if (!dmaDev || !dmaDev->cfg) @@ -158,8 +154,7 @@ whal_Error whal_Stm32wba_Gpdma_Init(whal_Dma *dmaDev) whal_Error whal_Stm32wba_Gpdma_Deinit(whal_Dma *dmaDev) { -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; size_t base = whal_Stm32wba_Gpdma_Dev.base; @@ -190,8 +185,7 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, const whal_Stm32wba_Gpdma_ChCfg *ccfg; size_t tr1, tr2; whal_Error err; -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; size_t base = whal_Stm32wba_Gpdma_Dev.base; @@ -275,8 +269,7 @@ whal_Error whal_Stm32wba_Gpdma_Configure(whal_Dma *dmaDev, size_t ch, whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) { -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; size_t base = whal_Stm32wba_Gpdma_Dev.base; @@ -307,8 +300,7 @@ whal_Error whal_Stm32wba_Gpdma_Start(whal_Dma *dmaDev, size_t ch) whal_Error whal_Stm32wba_Gpdma_Stop(whal_Dma *dmaDev, size_t ch) { -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE const whal_Stm32wba_Gpdma_Cfg *cfg = (const whal_Stm32wba_Gpdma_Cfg *)whal_Stm32wba_Gpdma_Dev.cfg; size_t base = whal_Stm32wba_Gpdma_Dev.base; @@ -338,8 +330,7 @@ void whal_Stm32wba_Gpdma_IRQHandler(whal_Dma *dmaDev, size_t ch, whal_Stm32wba_Gpdma_Callback cb, void *ctx) { size_t sr; -#if defined(WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_GPDMA_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WBA_GPDMA_SINGLE_INSTANCE size_t base = whal_Stm32wba_Gpdma_Dev.base; (void)dmaDev; #else @@ -370,8 +361,7 @@ void whal_Stm32wba_Gpdma_IRQHandler(whal_Dma *dmaDev, size_t ch, } } -#if !defined(WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_GPDMA_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WBA_GPDMA_DIRECT_API_MAPPING const whal_DmaDriver whal_Stm32wba_Gpdma_Driver = { .Init = whal_Stm32wba_Gpdma_Init, .Deinit = whal_Stm32wba_Gpdma_Deinit, diff --git a/src/flash/stm32f0_flash.c b/src/flash/stm32f0_flash.c index e69d240..83de759 100644 --- a/src/flash/stm32f0_flash.c +++ b/src/flash/stm32f0_flash.c @@ -61,8 +61,7 @@ const whal_Flash whal_Stm32f0_Flash_Dev = WHAL_CFG_STM32F0_FLASH_DEV; #define FLASH_AR_REG 0x14 -#if defined(WHAL_CFG_STM32F0_FLASH_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_FLASH_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32F0_FLASH_DIRECT_API_MAPPING #define whal_Stm32f0_Flash_Init whal_Flash_Init #define whal_Stm32f0_Flash_Deinit whal_Flash_Deinit #define whal_Stm32f0_Flash_Lock whal_Flash_Lock @@ -244,8 +243,7 @@ whal_Error whal_Stm32f0_Flash_Ext_SetLatency(whal_Flash *flashDev, return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32F0_FLASH_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_FLASH_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32F0_FLASH_DIRECT_API_MAPPING const whal_FlashDriver whal_Stm32f0_Flash_Driver = { .Init = whal_Stm32f0_Flash_Init, .Deinit = whal_Stm32f0_Flash_Deinit, diff --git a/src/flash/stm32f3_flash.c b/src/flash/stm32f3_flash.c index 01aee7d..181d809 100644 --- a/src/flash/stm32f3_flash.c +++ b/src/flash/stm32f3_flash.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_FLASH_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F0_FLASH_DIRECT_API_MAPPING +#endif #include "stm32f0_flash.c" diff --git a/src/flash/stm32u5_flash.c b/src/flash/stm32u5_flash.c new file mode 100644 index 0000000..797ddd4 --- /dev/null +++ b/src/flash/stm32u5_flash.c @@ -0,0 +1,323 @@ +/* stm32u5_flash.c + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#include +#include "board.h" /* provides WHAL_CFG_STM32U5_FLASH_DEV initializer */ +#include +#include +#include +#include +#include +#include + +const whal_Flash whal_Stm32u5_Flash_Dev = WHAL_CFG_STM32U5_FLASH_DEV; + +#ifdef WHAL_CFG_STM32U5_FLASH_DIRECT_API_MAPPING +#define whal_Stm32u5_Flash_Init whal_Flash_Init +#define whal_Stm32u5_Flash_Deinit whal_Flash_Deinit +#define whal_Stm32u5_Flash_Lock whal_Flash_Lock +#define whal_Stm32u5_Flash_Unlock whal_Flash_Unlock +#define whal_Stm32u5_Flash_Read whal_Flash_Read +#define whal_Stm32u5_Flash_Write whal_Flash_Write +#define whal_Stm32u5_Flash_Erase whal_Flash_Erase +#endif /* WHAL_CFG_STM32U5_FLASH_DIRECT_API_MAPPING */ + +/* + * STM32U5 Flash Register Definitions (RM0456 section 7.9) + * + * Flash interface base: 0x40022000 + */ + +/* Access Control Register */ +#define FLASH_ACR_REG 0x000 +#define FLASH_ACR_LATENCY_Msk 0x0FUL + +/* Non-Secure Key Register - unlock sequence */ +#define FLASH_NSKEYR_REG 0x008 + +/* Non-Secure Status Register (RM0456 section 7.9.7) */ +#define FLASH_NSSR_REG 0x020 +#define FLASH_NSSR_EOP_Pos 0 +#define FLASH_NSSR_EOP_Msk (1UL << FLASH_NSSR_EOP_Pos) +#define FLASH_NSSR_OPERR_Pos 1 +#define FLASH_NSSR_OPERR_Msk (1UL << FLASH_NSSR_OPERR_Pos) +#define FLASH_NSSR_PROGERR_Pos 3 +#define FLASH_NSSR_PROGERR_Msk (1UL << FLASH_NSSR_PROGERR_Pos) +#define FLASH_NSSR_WRPERR_Pos 4 +#define FLASH_NSSR_WRPERR_Msk (1UL << FLASH_NSSR_WRPERR_Pos) +#define FLASH_NSSR_PGAERR_Pos 5 +#define FLASH_NSSR_PGAERR_Msk (1UL << FLASH_NSSR_PGAERR_Pos) +#define FLASH_NSSR_SIZERR_Pos 6 +#define FLASH_NSSR_SIZERR_Msk (1UL << FLASH_NSSR_SIZERR_Pos) +#define FLASH_NSSR_PGSERR_Pos 7 +#define FLASH_NSSR_PGSERR_Msk (1UL << FLASH_NSSR_PGSERR_Pos) +#define FLASH_NSSR_OPTWERR_Pos 13 +#define FLASH_NSSR_OPTWERR_Msk (1UL << FLASH_NSSR_OPTWERR_Pos) +#define FLASH_NSSR_BSY_Pos 16 +#define FLASH_NSSR_BSY_Msk (1UL << FLASH_NSSR_BSY_Pos) +#define FLASH_NSSR_WDW_Pos 17 +#define FLASH_NSSR_WDW_Msk (1UL << FLASH_NSSR_WDW_Pos) + +#define FLASH_NSSR_ALL_ERR (FLASH_NSSR_OPERR_Msk | FLASH_NSSR_PROGERR_Msk | \ + FLASH_NSSR_WRPERR_Msk | FLASH_NSSR_PGAERR_Msk | \ + FLASH_NSSR_SIZERR_Msk | FLASH_NSSR_PGSERR_Msk | \ + FLASH_NSSR_OPTWERR_Msk) + +/* Non-Secure Control Register (RM0456 section 7.9.9) + * Bit layout differs from STM32WBA: PNB is 8 bits at 10:3, BKER at 11. */ +#define FLASH_NSCR_REG 0x028 +#define FLASH_NSCR_PG_Pos 0 +#define FLASH_NSCR_PG_Msk (1UL << FLASH_NSCR_PG_Pos) +#define FLASH_NSCR_PER_Pos 1 +#define FLASH_NSCR_PER_Msk (1UL << FLASH_NSCR_PER_Pos) +#define FLASH_NSCR_MER1_Pos 2 +#define FLASH_NSCR_MER1_Msk (1UL << FLASH_NSCR_MER1_Pos) +#define FLASH_NSCR_PNB_Pos 3 +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) +#define FLASH_NSCR_BKER_Pos 11 +#define FLASH_NSCR_BKER_Msk (1UL << FLASH_NSCR_BKER_Pos) +#define FLASH_NSCR_BWR_Pos 14 +#define FLASH_NSCR_BWR_Msk (1UL << FLASH_NSCR_BWR_Pos) +#define FLASH_NSCR_MER2_Pos 15 +#define FLASH_NSCR_MER2_Msk (1UL << FLASH_NSCR_MER2_Pos) +#define FLASH_NSCR_STRT_Pos 16 +#define FLASH_NSCR_STRT_Msk (1UL << FLASH_NSCR_STRT_Pos) +#define FLASH_NSCR_OPTSTRT_Pos 17 +#define FLASH_NSCR_OPTSTRT_Msk (1UL << FLASH_NSCR_OPTSTRT_Pos) +#define FLASH_NSCR_LOCK_Pos 31 +#define FLASH_NSCR_LOCK_Msk (1UL << FLASH_NSCR_LOCK_Pos) + +/* Unlock keys */ +#define FLASH_KEY1 0x45670123UL +#define FLASH_KEY2 0xCDEF89ABUL + +whal_Error whal_Stm32u5_Flash_Init(whal_Flash *flashDev) +{ + (void)flashDev; + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32u5_Flash_Deinit(whal_Flash *flashDev) +{ + (void)flashDev; + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32u5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len) +{ + size_t base = whal_Stm32u5_Flash_Dev.base; + (void)flashDev; + (void)addr; + (void)len; + + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_LOCK_Msk, + whal_SetBits(FLASH_NSCR_LOCK_Msk, FLASH_NSCR_LOCK_Pos, 1)); + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32u5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len) +{ + size_t base = whal_Stm32u5_Flash_Dev.base; + (void)flashDev; + (void)addr; + (void)len; + + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY1); + whal_Reg_Write(base, FLASH_NSKEYR_REG, FLASH_KEY2); + + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32u5_Flash_Read(whal_Flash *flashDev, size_t addr, + void *data, size_t dataSz) +{ + const whal_Stm32u5_Flash_Cfg *cfg = + (const whal_Stm32u5_Flash_Cfg *)whal_Stm32u5_Flash_Dev.cfg; + uint8_t *dataBuf = (uint8_t *)data; + (void)flashDev; + + if (!data) + return WHAL_EINVAL; + + if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) + return WHAL_EINVAL; + + uint8_t *flashAddr = (uint8_t *)addr; + for (size_t i = 0; i < dataSz; ++i) + dataBuf[i] = flashAddr[i]; + + return WHAL_SUCCESS; +} + +static whal_Error WaitNotBusy(size_t base, whal_Timeout *timeout) +{ + return whal_Reg_ReadPoll(base, FLASH_NSSR_REG, + FLASH_NSSR_BSY_Msk | FLASH_NSSR_WDW_Msk, + 0, timeout); +} + +static whal_Error CheckAndClearErrors(size_t base) +{ + size_t sr = whal_Reg_Read(base, FLASH_NSSR_REG); + if (sr & FLASH_NSSR_ALL_ERR) { + whal_Reg_Write(base, FLASH_NSSR_REG, sr & FLASH_NSSR_ALL_ERR); + return WHAL_EHARDWARE; + } + return WHAL_SUCCESS; +} + +whal_Error whal_Stm32u5_Flash_Write(whal_Flash *flashDev, size_t addr, + const void *data, size_t dataSz) +{ + const whal_Stm32u5_Flash_Cfg *cfg = + (const whal_Stm32u5_Flash_Cfg *)whal_Stm32u5_Flash_Dev.cfg; + size_t base = whal_Stm32u5_Flash_Dev.base; + const uint8_t *dataBuf = (const uint8_t *)data; + whal_Error err; + (void)flashDev; + + if (!data) + return WHAL_EINVAL; + + /* Address and size must be 16-byte aligned (128-bit flash-word). */ + if ((addr & 0xF) || (dataSz & 0xF)) + return WHAL_EINVAL; + + if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) + return WHAL_EINVAL; + + err = WaitNotBusy(base, cfg->timeout); + if (err) + return err; + + /* Clear error flags */ + whal_Reg_Write(base, FLASH_NSSR_REG, + whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + + /* Enable programming */ + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, + whal_SetBits(FLASH_NSCR_PG_Msk, FLASH_NSCR_PG_Pos, 1)); + + /* Program in 128-bit (16 byte) flash-word chunks. The destination must + * be volatile — the flash controller's write FIFO requires exactly 4 + * sequential 32-bit stores per flash-word; the compiler is free to + * reorder or merge non-volatile stores into LDM/STM or memcpy. */ + for (size_t i = 0; i < dataSz; i += 16) { + volatile uint32_t *flashAddr = (volatile uint32_t *)(addr + i); + const uint32_t *dataAddr = (const uint32_t *)(dataBuf + i); + + flashAddr[0] = dataAddr[0]; + flashAddr[1] = dataAddr[1]; + flashAddr[2] = dataAddr[2]; + flashAddr[3] = dataAddr[3]; + + err = WaitNotBusy(base, cfg->timeout); + if (err) + goto cleanup; + + err = CheckAndClearErrors(base); + if (err) + goto cleanup; + } + +cleanup: + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PG_Msk, 0); + return err; +} + +whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz) +{ + const whal_Stm32u5_Flash_Cfg *cfg = + (const whal_Stm32u5_Flash_Cfg *)whal_Stm32u5_Flash_Dev.cfg; + size_t base = whal_Stm32u5_Flash_Dev.base; + size_t bankSize = cfg->bankSize ? cfg->bankSize : WHAL_STM32U5_FLASH_BANK_SIZE; + whal_Error err; + size_t offset, startGlobal, endGlobal; + (void)flashDev; + + if (dataSz == 0) + return WHAL_SUCCESS; + + if (addr < cfg->startAddr || addr + dataSz > cfg->startAddr + cfg->size) + return WHAL_EINVAL; + + err = WaitNotBusy(base, cfg->timeout); + if (err) + return err; + + /* Clear error flags */ + whal_Reg_Write(base, FLASH_NSSR_REG, + whal_Reg_Read(base, FLASH_NSSR_REG) & FLASH_NSSR_ALL_ERR); + + offset = addr - cfg->startAddr; + startGlobal = offset / WHAL_STM32U5_FLASH_PAGE_SIZE; + endGlobal = (offset + dataSz - 1) / WHAL_STM32U5_FLASH_PAGE_SIZE; + + for (size_t global = startGlobal; global <= endGlobal; global++) { + size_t pagesPerBank = bankSize / WHAL_STM32U5_FLASH_PAGE_SIZE; + size_t bank = global / pagesPerBank; + size_t page = global % pagesPerBank; + + /* Configure page erase: PER=1, BKER=bank, PNB=page, STRT=1 */ + whal_Reg_Update(base, FLASH_NSCR_REG, + FLASH_NSCR_PER_Msk | FLASH_NSCR_BKER_Msk | + FLASH_NSCR_PNB_Msk, + whal_SetBits(FLASH_NSCR_PER_Msk, FLASH_NSCR_PER_Pos, 1) | + whal_SetBits(FLASH_NSCR_BKER_Msk, FLASH_NSCR_BKER_Pos, bank) | + whal_SetBits(FLASH_NSCR_PNB_Msk, FLASH_NSCR_PNB_Pos, page)); + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_STRT_Msk, + whal_SetBits(FLASH_NSCR_STRT_Msk, FLASH_NSCR_STRT_Pos, 1)); + + err = WaitNotBusy(base, cfg->timeout); + if (err) + goto cleanup; + + err = CheckAndClearErrors(base); + if (err) + goto cleanup; + } + +cleanup: + whal_Reg_Update(base, FLASH_NSCR_REG, FLASH_NSCR_PER_Msk, 0); + return err; +} + +whal_Error whal_Stm32u5_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency) +{ + size_t base = whal_Stm32u5_Flash_Dev.base; + (void)flashDev; + + whal_Reg_Update(base, FLASH_ACR_REG, FLASH_ACR_LATENCY_Msk, latency); + return WHAL_SUCCESS; +} + +#ifndef WHAL_CFG_STM32U5_FLASH_DIRECT_API_MAPPING +const whal_FlashDriver whal_Stm32u5_Flash_Driver = { + .Init = whal_Stm32u5_Flash_Init, + .Deinit = whal_Stm32u5_Flash_Deinit, + .Lock = whal_Stm32u5_Flash_Lock, + .Unlock = whal_Stm32u5_Flash_Unlock, + .Read = whal_Stm32u5_Flash_Read, + .Write = whal_Stm32u5_Flash_Write, + .Erase = whal_Stm32u5_Flash_Erase, +}; +#endif /* !WHAL_CFG_STM32U5_FLASH_DIRECT_API_MAPPING */ diff --git a/src/gpio/stm32c0_gpio.c b/src/gpio/stm32c0_gpio.c index b96f820..fd7ff99 100644 --- a/src/gpio/stm32c0_gpio.c +++ b/src/gpio/stm32c0_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32f0_gpio.c b/src/gpio/stm32f0_gpio.c index 75c76be..8ee6840 100644 --- a/src/gpio/stm32f0_gpio.c +++ b/src/gpio/stm32f0_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F0_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32f3_gpio.c b/src/gpio/stm32f3_gpio.c index bc3eba5..3e2d55e 100644 --- a/src/gpio/stm32f3_gpio.c +++ b/src/gpio/stm32f3_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32f4_gpio.c b/src/gpio/stm32f4_gpio.c index 3c7579d..a80d1eb 100644 --- a/src/gpio/stm32f4_gpio.c +++ b/src/gpio/stm32f4_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F4_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32h5_gpio.c b/src/gpio/stm32h5_gpio.c index 59ac7d4..99a85f7 100644 --- a/src/gpio/stm32h5_gpio.c +++ b/src/gpio/stm32h5_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32l1_gpio.c b/src/gpio/stm32l1_gpio.c index bb68aa1..8e592d8 100644 --- a/src/gpio/stm32l1_gpio.c +++ b/src/gpio/stm32l1_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32L1_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32n6_gpio.c b/src/gpio/stm32n6_gpio.c index bb019ac..365340a 100644 --- a/src/gpio/stm32n6_gpio.c +++ b/src/gpio/stm32n6_gpio.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif #include "stm32wb_gpio.c" diff --git a/src/gpio/stm32u5_gpio.c b/src/gpio/stm32u5_gpio.c new file mode 100644 index 0000000..0f10d65 --- /dev/null +++ b/src/gpio/stm32u5_gpio.c @@ -0,0 +1,5 @@ +#ifdef WHAL_CFG_STM32U5_GPIO_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING +#endif + +#include "stm32wb_gpio.c" diff --git a/src/gpio/stm32wb_gpio.c b/src/gpio/stm32wb_gpio.c index cab4819..2e39abd 100644 --- a/src/gpio/stm32wb_gpio.c +++ b/src/gpio/stm32wb_gpio.c @@ -56,14 +56,7 @@ const whal_Gpio whal_Stm32wb_Gpio_Dev = WHAL_CFG_STM32WB_GPIO_DEV; /* Alternate function high register - 4 bits per pin for pins 8-15 */ #define GPIO_ALTFNH_REG 0x24 -#if defined(WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F4_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F0_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32L1_GPIO_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_GPIO_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING #define whal_Stm32wb_Gpio_Init whal_Gpio_Init #define whal_Stm32wb_Gpio_Deinit whal_Gpio_Deinit #define whal_Stm32wb_Gpio_Get whal_Gpio_Get @@ -196,13 +189,7 @@ whal_Error whal_Stm32wb_Gpio_Set(whal_Gpio *gpioDev, size_t pin, size_t value) return whal_Stm32wb_Gpio_SetOrGet(gpioDev, pin, &value, 1); } -#if !defined(WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F4_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32H5_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32C0_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F0_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_GPIO_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32L1_GPIO_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WB_GPIO_DIRECT_API_MAPPING const whal_GpioDriver whal_Stm32wb_Gpio_Driver = { .Init = whal_Stm32wb_Gpio_Init, .Deinit = whal_Stm32wb_Gpio_Deinit, diff --git a/src/i2c/stm32f0_i2c.c b/src/i2c/stm32f0_i2c.c index b728c80..89a8710 100644 --- a/src/i2c/stm32f0_i2c.c +++ b/src/i2c/stm32f0_i2c.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F0_I2C_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE +#endif #include "stm32wb_i2c.c" diff --git a/src/i2c/stm32f3_i2c.c b/src/i2c/stm32f3_i2c.c index d911984..7c995d5 100644 --- a/src/i2c/stm32f3_i2c.c +++ b/src/i2c/stm32f3_i2c.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_I2C_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE +#endif #include "stm32wb_i2c.c" diff --git a/src/i2c/stm32n6_i2c.c b/src/i2c/stm32n6_i2c.c index 0da576e..9a2cb3a 100644 --- a/src/i2c/stm32n6_i2c.c +++ b/src/i2c/stm32n6_i2c.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_I2C_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE +#endif #include "stm32wb_i2c.c" diff --git a/src/i2c/stm32u5_i2c.c b/src/i2c/stm32u5_i2c.c new file mode 100644 index 0000000..eac7d38 --- /dev/null +++ b/src/i2c/stm32u5_i2c.c @@ -0,0 +1,7 @@ +#ifdef WHAL_CFG_STM32U5_I2C_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_I2C_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE +#endif +#include "stm32wb_i2c.c" diff --git a/src/i2c/stm32wb_i2c.c b/src/i2c/stm32wb_i2c.c index 519b107..86e6338 100644 --- a/src/i2c/stm32wb_i2c.c +++ b/src/i2c/stm32wb_i2c.c @@ -20,10 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32wb_I2c_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -148,10 +145,7 @@ #define I2C_FMP_TLOW_NS 500 /* Fast mode plus tLOW min */ #define I2C_FMP_THIGH_NS 260 /* Fast mode plus tHIGH min */ -#if defined(WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F0_I2C_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_I2C_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_I2C_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING #define whal_Stm32wb_I2c_Init whal_I2c_Init #define whal_Stm32wb_I2c_Deinit whal_I2c_Deinit #define whal_Stm32wb_I2c_StartCom whal_I2c_StartCom @@ -159,10 +153,7 @@ #define whal_Stm32wb_I2c_Transfer whal_I2c_Transfer #endif /* WHAL_CFG_I2C_API_MAPPING */ -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE const whal_I2c whal_Stm32wb_I2c_Dev = WHAL_CFG_STM32WB_I2C_DEV; #endif @@ -405,10 +396,7 @@ static whal_Error Stm32wb_I2c_TransferMsg(size_t base, whal_I2c_Msg *msg, whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) { -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE size_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else @@ -440,10 +428,7 @@ whal_Error whal_Stm32wb_I2c_Init(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) { -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE size_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else @@ -466,10 +451,7 @@ whal_Error whal_Stm32wb_I2c_Deinit(whal_I2c *i2cDev) whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) { uint32_t cr2 = 0; -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE whal_Stm32wb_I2c_Cfg *cfg = (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; size_t base = whal_Stm32wb_I2c_Dev.base; @@ -491,10 +473,7 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) return WHAL_EINVAL; } -#if !defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifndef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE base = i2cDev->base; cfg = (whal_Stm32wb_I2c_Cfg *)i2cDev->cfg; #endif @@ -529,10 +508,7 @@ whal_Error whal_Stm32wb_I2c_StartCom(whal_I2c *i2cDev, whal_I2c_ComCfg *comCfg) whal_Error whal_Stm32wb_I2c_EndCom(whal_I2c *i2cDev) { -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE size_t base = whal_Stm32wb_I2c_Dev.base; (void)i2cDev; #else @@ -556,10 +532,7 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, size_t numMsgs) { whal_Error err; -#if defined(WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_I2C_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_I2C_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_I2C_SINGLE_INSTANCE whal_Stm32wb_I2c_Cfg *cfg = (whal_Stm32wb_I2c_Cfg *)whal_Stm32wb_I2c_Dev.cfg; size_t base = whal_Stm32wb_I2c_Dev.base; @@ -602,10 +575,7 @@ whal_Error whal_Stm32wb_I2c_Transfer(whal_I2c *i2cDev, whal_I2c_Msg *msgs, return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F0_I2C_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_I2C_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_I2C_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WB_I2C_DIRECT_API_MAPPING const whal_I2cDriver whal_Stm32wb_I2c_Driver = { .Init = whal_Stm32wb_I2c_Init, .Deinit = whal_Stm32wb_I2c_Deinit, diff --git a/src/rng/stm32n6_rng.c b/src/rng/stm32n6_rng.c index 552c941..d236d0c 100644 --- a/src/rng/stm32n6_rng.c +++ b/src/rng/stm32n6_rng.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_RNG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING +#endif #include "stm32wba_rng.c" diff --git a/src/rng/stm32u5_rng.c b/src/rng/stm32u5_rng.c new file mode 100644 index 0000000..93a5eb9 --- /dev/null +++ b/src/rng/stm32u5_rng.c @@ -0,0 +1,4 @@ +#ifdef WHAL_CFG_STM32U5_RNG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING +#endif +#include "stm32wba_rng.c" diff --git a/src/rng/stm32wba_rng.c b/src/rng/stm32wba_rng.c index 9033866..179c197 100644 --- a/src/rng/stm32wba_rng.c +++ b/src/rng/stm32wba_rng.c @@ -82,8 +82,7 @@ const whal_Rng whal_Stm32wba_Rng_Dev = WHAL_CFG_STM32WBA_RNG_DEV; #define RNG_CR_CONFIG_C (whal_SetBits(RNG_CR_RNG_CONFIG1_Msk, RNG_CR_RNG_CONFIG1_Pos, 0x0F) | \ whal_SetBits(RNG_CR_RNG_CONFIG3_Msk, RNG_CR_RNG_CONFIG3_Pos, 0x0D)) -#if defined(WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_RNG_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING #define whal_Stm32wba_Rng_Init whal_Rng_Init #define whal_Stm32wba_Rng_Deinit whal_Rng_Deinit #define whal_Stm32wba_Rng_Generate whal_Rng_Generate @@ -169,8 +168,7 @@ whal_Error whal_Stm32wba_Rng_Generate(whal_Rng *rngDev, void *rngData, size_t rn return err; } -#if !defined(WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_RNG_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WBA_RNG_DIRECT_API_MAPPING const whal_RngDriver whal_Stm32wba_Rng_Driver = { .Init = whal_Stm32wba_Rng_Init, .Deinit = whal_Stm32wba_Rng_Deinit, diff --git a/src/spi/stm32c0_spi.c b/src/spi/stm32c0_spi.c index 2237f9d..51eaa2a 100644 --- a/src/spi/stm32c0_spi.c +++ b/src/spi/stm32c0_spi.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE +#endif #include "stm32wb_spi.c" diff --git a/src/spi/stm32f0_spi.c b/src/spi/stm32f0_spi.c index b58f093..0dd69ac 100644 --- a/src/spi/stm32f0_spi.c +++ b/src/spi/stm32f0_spi.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F0_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE +#endif #include "stm32wb_spi.c" diff --git a/src/spi/stm32f3_spi.c b/src/spi/stm32f3_spi.c index 9174eca..5cb8ff1 100644 --- a/src/spi/stm32f3_spi.c +++ b/src/spi/stm32f3_spi.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE +#endif #include "stm32wb_spi.c" diff --git a/src/spi/stm32f4_spi.c b/src/spi/stm32f4_spi.c index f926f55..d5a7a74 100644 --- a/src/spi/stm32f4_spi.c +++ b/src/spi/stm32f4_spi.c @@ -20,8 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32f4_Spi_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -81,8 +80,7 @@ /* Data Register - 8/16-bit access */ #define SPI_DR_REG 0x0C -#if defined(WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32L1_SPI_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING #define whal_Stm32f4_Spi_Init whal_Spi_Init #define whal_Stm32f4_Spi_Deinit whal_Spi_Deinit #define whal_Stm32f4_Spi_StartCom whal_Spi_StartCom @@ -90,8 +88,7 @@ #define whal_Stm32f4_Spi_SendRecv whal_Spi_SendRecv #endif /* WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING */ -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE const whal_Spi whal_Stm32f4_Spi_Dev = WHAL_CFG_STM32F4_SPI_DEV; #endif @@ -117,8 +114,7 @@ static uint32_t whal_Stm32f4_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE size_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else @@ -142,8 +138,7 @@ whal_Error whal_Stm32f4_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE size_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else @@ -165,8 +160,7 @@ whal_Error whal_Stm32f4_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { uint32_t cpol, cpha, br; -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE whal_Stm32f4_Spi_Cfg *cfg = (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; size_t base = whal_Stm32f4_Spi_Dev.base; @@ -189,8 +183,7 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; -#if !defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifndef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE base = spiDev->base; cfg = (whal_Stm32f4_Spi_Cfg *)spiDev->cfg; #endif @@ -220,8 +213,7 @@ whal_Error whal_Stm32f4_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32f4_Spi_EndCom(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE size_t base = whal_Stm32f4_Spi_Dev.base; (void)spiDev; #else @@ -249,8 +241,7 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, size_t totalLen; whal_Error err; uint8_t txByte; -#if defined(WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE whal_Stm32f4_Spi_Cfg *cfg = (whal_Stm32f4_Spi_Cfg *)whal_Stm32f4_Spi_Dev.cfg; size_t base = whal_Stm32f4_Spi_Dev.base; @@ -301,8 +292,7 @@ whal_Error whal_Stm32f4_Spi_SendRecv(whal_Spi *spiDev, cfg->timeout); } -#if !defined(WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32L1_SPI_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING const whal_SpiDriver whal_Stm32f4_Spi_Driver = { .Init = whal_Stm32f4_Spi_Init, .Deinit = whal_Stm32f4_Spi_Deinit, diff --git a/src/spi/stm32h5_spi.c b/src/spi/stm32h5_spi.c index d553a9c..2e3dfdc 100644 --- a/src/spi/stm32h5_spi.c +++ b/src/spi/stm32h5_spi.c @@ -20,9 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32h5_Spi_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -115,8 +113,7 @@ #define SPI_TXDR_REG 0x020 #define SPI_RXDR_REG 0x030 -#if defined(WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_SPI_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING #define whal_Stm32h5_Spi_Init whal_Spi_Init #define whal_Stm32h5_Spi_Deinit whal_Spi_Deinit #define whal_Stm32h5_Spi_StartCom whal_Spi_StartCom @@ -124,9 +121,7 @@ #define whal_Stm32h5_Spi_SendRecv whal_Spi_SendRecv #endif /* WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING */ -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE const whal_Spi whal_Stm32h5_Spi_Dev = WHAL_CFG_STM32H5_SPI_DEV; #endif @@ -149,9 +144,7 @@ static uint32_t Stm32h5_Spi_CalcMbr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE size_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else @@ -181,9 +174,7 @@ whal_Error whal_Stm32h5_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE size_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else @@ -204,9 +195,7 @@ whal_Error whal_Stm32h5_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { uint32_t cpol, cpha, mbr, dsize, fthlv; -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE whal_Stm32h5_Spi_Cfg *cfg = (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; size_t base = whal_Stm32h5_Spi_Dev.base; @@ -228,9 +217,7 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) if (comCfg->mode > 3 || comCfg->dataLines != 1 || comCfg->freq == 0) return WHAL_EINVAL; -#if !defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifndef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE base = spiDev->base; cfg = (whal_Stm32h5_Spi_Cfg *)spiDev->cfg; #endif @@ -274,9 +261,7 @@ whal_Error whal_Stm32h5_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32h5_Spi_EndCom(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE size_t base = whal_Stm32h5_Spi_Dev.base; (void)spiDev; #else @@ -308,9 +293,7 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, size_t totalLen; whal_Error err; uint8_t txByte; -#if defined(WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE whal_Stm32h5_Spi_Cfg *cfg = (whal_Stm32h5_Spi_Cfg *)whal_Stm32h5_Spi_Dev.cfg; size_t base = whal_Stm32h5_Spi_Dev.base; @@ -359,8 +342,7 @@ whal_Error whal_Stm32h5_Spi_SendRecv(whal_Spi *spiDev, return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_SPI_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING const whal_SpiDriver whal_Stm32h5_Spi_Driver = { .Init = whal_Stm32h5_Spi_Init, .Deinit = whal_Stm32h5_Spi_Deinit, diff --git a/src/spi/stm32l1_spi.c b/src/spi/stm32l1_spi.c index df88281..c5159f0 100644 --- a/src/spi/stm32l1_spi.c +++ b/src/spi/stm32l1_spi.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32L1_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F4_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32L1_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32F4_SPI_SINGLE_INSTANCE +#endif #include "stm32f4_spi.c" diff --git a/src/spi/stm32n6_spi.c b/src/spi/stm32n6_spi.c index 4944c71..a842dea 100644 --- a/src/spi/stm32n6_spi.c +++ b/src/spi/stm32n6_spi.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE +#endif #include "stm32h5_spi.c" diff --git a/src/spi/stm32u5_spi.c b/src/spi/stm32u5_spi.c new file mode 100644 index 0000000..c0b2e96 --- /dev/null +++ b/src/spi/stm32u5_spi.c @@ -0,0 +1,7 @@ +#ifdef WHAL_CFG_STM32U5_SPI_DIRECT_API_MAPPING +#define WHAL_CFG_STM32H5_SPI_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE +#endif +#include "stm32h5_spi.c" diff --git a/src/spi/stm32wb_spi.c b/src/spi/stm32wb_spi.c index 3cc609b..92ed7f8 100644 --- a/src/spi/stm32wb_spi.c +++ b/src/spi/stm32wb_spi.c @@ -20,10 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32wb_Spi_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -87,10 +84,7 @@ #define SPI_DR_Pos 0 #define SPI_DR_Msk (WHAL_BITMASK(8) << SPI_DR_Pos) -#if defined(WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F0_SPI_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_SPI_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING #define whal_Stm32wb_Spi_Init whal_Spi_Init #define whal_Stm32wb_Spi_Deinit whal_Spi_Deinit #define whal_Stm32wb_Spi_StartCom whal_Spi_StartCom @@ -98,10 +92,7 @@ #define whal_Stm32wb_Spi_SendRecv whal_Spi_SendRecv #endif /* WHAL_CFG_SPI_API_MAPPING */ -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE const whal_Spi whal_Stm32wb_Spi_Dev = WHAL_CFG_STM32WB_SPI_DEV; #endif @@ -128,10 +119,7 @@ static uint32_t whal_Stm32wb_Spi_CalcBr(size_t pclk, uint32_t targetBaud) whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE size_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else @@ -156,10 +144,7 @@ whal_Error whal_Stm32wb_Spi_Init(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE size_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else @@ -182,10 +167,7 @@ whal_Error whal_Stm32wb_Spi_Deinit(whal_Spi *spiDev) whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) { uint32_t cpol, cpha, br, ds, frxth; -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE whal_Stm32wb_Spi_Cfg *cfg = (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; size_t base = whal_Stm32wb_Spi_Dev.base; @@ -212,10 +194,7 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) return WHAL_EINVAL; } -#if !defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) && \ - !defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifndef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE base = spiDev->base; cfg = (whal_Stm32wb_Spi_Cfg *)spiDev->cfg; #endif @@ -253,10 +232,7 @@ whal_Error whal_Stm32wb_Spi_StartCom(whal_Spi *spiDev, whal_Spi_ComCfg *comCfg) whal_Error whal_Stm32wb_Spi_EndCom(whal_Spi *spiDev) { -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE size_t base = whal_Stm32wb_Spi_Dev.base; (void)spiDev; #else @@ -285,10 +261,7 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, size_t totalLen; whal_Error err; uint8_t txByte; -#if defined(WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F0_SPI_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_SPI_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_SPI_SINGLE_INSTANCE whal_Stm32wb_Spi_Cfg *cfg = (whal_Stm32wb_Spi_Cfg *)whal_Stm32wb_Spi_Dev.cfg; size_t base = whal_Stm32wb_Spi_Dev.base; @@ -341,10 +314,7 @@ whal_Error whal_Stm32wb_Spi_SendRecv(whal_Spi *spiDev, cfg->timeout); } -#if !defined(WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32C0_SPI_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F0_SPI_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_SPI_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WB_SPI_DIRECT_API_MAPPING const whal_SpiDriver whal_Stm32wb_Spi_Driver = { .Init = whal_Stm32wb_Spi_Init, .Deinit = whal_Stm32wb_Spi_Deinit, diff --git a/src/spi/stm32wba_spi.c b/src/spi/stm32wba_spi.c index 2954b02..a8386ff 100644 --- a/src/spi/stm32wba_spi.c +++ b/src/spi/stm32wba_spi.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32WBA_SPI_SINGLE_INSTANCE +#define WHAL_CFG_STM32H5_SPI_SINGLE_INSTANCE +#endif #include "stm32h5_spi.c" diff --git a/src/uart/stm32c0_uart.c b/src/uart/stm32c0_uart.c index 3c09e4f..4835e10 100644 --- a/src/uart/stm32c0_uart.c +++ b/src/uart/stm32c0_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32C0_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE +#endif #include "stm32wb_uart.c" diff --git a/src/uart/stm32f0_uart.c b/src/uart/stm32f0_uart.c index 16adef8..73a989c 100644 --- a/src/uart/stm32f0_uart.c +++ b/src/uart/stm32f0_uart.c @@ -20,8 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32f0_Uart_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -59,8 +58,7 @@ #define UART_TDR_Pos 0 #define UART_TDR_Msk (WHAL_BITMASK(9) << UART_TDR_Pos) -#if defined(WHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_UART_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING #define whal_Stm32f0_Uart_Init whal_Uart_Init #define whal_Stm32f0_Uart_Deinit whal_Uart_Deinit #define whal_Stm32f0_Uart_Send whal_Uart_Send @@ -69,15 +67,13 @@ #define whal_Stm32f0_Uart_RecvAsync whal_Uart_RecvAsync #endif -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Uart whal_Stm32f0_Uart_Dev = WHAL_CFG_STM32F0_UART_DEV; #endif whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) { -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; size_t base = whal_Stm32f0_Uart_Dev.base; @@ -108,8 +104,7 @@ whal_Error whal_Stm32f0_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f0_Uart_Deinit(whal_Uart *uartDev) { -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE size_t base = whal_Stm32f0_Uart_Dev.base; (void)uartDev; #else @@ -137,8 +132,7 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { const uint8_t *buf = data; -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; size_t base = whal_Stm32f0_Uart_Dev.base; @@ -174,8 +168,7 @@ whal_Error whal_Stm32f0_Uart_Send(whal_Uart *uartDev, const void *data, whal_Error whal_Stm32f0_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { uint8_t *buf = data; -#if defined(WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE const whal_Stm32f0_Uart_Cfg *cfg = (const whal_Stm32f0_Uart_Cfg *)whal_Stm32f0_Uart_Dev.cfg; size_t base = whal_Stm32f0_Uart_Dev.base; @@ -227,8 +220,7 @@ whal_Error whal_Stm32f0_Uart_RecvAsync(whal_Uart *uartDev, void *data, return WHAL_ENOTSUP; } -#if !defined(WHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_UART_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING const whal_UartDriver whal_Stm32f0_Uart_Driver = { .Init = whal_Stm32f0_Uart_Init, .Deinit = whal_Stm32f0_Uart_Deinit, diff --git a/src/uart/stm32f3_uart.c b/src/uart/stm32f3_uart.c index ce00808..4984bf6 100644 --- a/src/uart/stm32f3_uart.c +++ b/src/uart/stm32f3_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F0_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32F3_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32F0_UART_SINGLE_INSTANCE +#endif #include "stm32f0_uart.c" diff --git a/src/uart/stm32f4_uart.c b/src/uart/stm32f4_uart.c index c1de6cd..6fe4ea0 100644 --- a/src/uart/stm32f4_uart.c +++ b/src/uart/stm32f4_uart.c @@ -20,8 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32f4_Uart_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -70,8 +69,7 @@ #define UART_CR1_UE_Pos 13 /* USART enable */ #define UART_CR1_UE_Msk (1UL << UART_CR1_UE_Pos) -#if defined(WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32L1_UART_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING #define whal_Stm32f4_Uart_Init whal_Uart_Init #define whal_Stm32f4_Uart_Deinit whal_Uart_Deinit #define whal_Stm32f4_Uart_Send whal_Uart_Send @@ -80,16 +78,14 @@ #define whal_Stm32f4_Uart_RecvAsync whal_Uart_RecvAsync #endif /* WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING */ -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Uart whal_Stm32f4_Uart_Dev = WHAL_CFG_STM32F4_UART_DEV; #endif whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) { uint32_t brr; -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; size_t base = whal_Stm32f4_Uart_Dev.base; @@ -124,8 +120,7 @@ whal_Error whal_Stm32f4_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) { -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE size_t base = whal_Stm32f4_Uart_Dev.base; (void)uartDev; #else @@ -155,8 +150,7 @@ whal_Error whal_Stm32f4_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32f4_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { const uint8_t *buf = data; -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; size_t base = whal_Stm32f4_Uart_Dev.base; @@ -195,8 +189,7 @@ whal_Error whal_Stm32f4_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { uint8_t *buf = data; size_t d; -#if defined(WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE const whal_Stm32f4_Uart_Cfg *cfg = (const whal_Stm32f4_Uart_Cfg *)whal_Stm32f4_Uart_Dev.cfg; size_t base = whal_Stm32f4_Uart_Dev.base; @@ -249,8 +242,7 @@ whal_Error whal_Stm32f4_Uart_RecvAsync(whal_Uart *uartDev, void *data, size_t da return WHAL_ENOTSUP; } -#if !defined(WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32L1_UART_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING const whal_UartDriver whal_Stm32f4_Uart_Driver = { .Init = whal_Stm32f4_Uart_Init, .Deinit = whal_Stm32f4_Uart_Deinit, diff --git a/src/uart/stm32h5_uart.c b/src/uart/stm32h5_uart.c index 992e881..088596e 100644 --- a/src/uart/stm32h5_uart.c +++ b/src/uart/stm32h5_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32H5_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE +#endif #include "stm32wb_uart.c" diff --git a/src/uart/stm32l1_uart.c b/src/uart/stm32l1_uart.c index a0bb782..c4970f0 100644 --- a/src/uart/stm32l1_uart.c +++ b/src/uart/stm32l1_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32L1_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F4_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32L1_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32F4_UART_SINGLE_INSTANCE +#endif #include "stm32f4_uart.c" diff --git a/src/uart/stm32n6_uart.c b/src/uart/stm32n6_uart.c index c8a9dac..57c9663 100644 --- a/src/uart/stm32n6_uart.c +++ b/src/uart/stm32n6_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE +#endif #include "stm32wb_uart.c" diff --git a/src/uart/stm32u5_uart.c b/src/uart/stm32u5_uart.c new file mode 100644 index 0000000..98775c4 --- /dev/null +++ b/src/uart/stm32u5_uart.c @@ -0,0 +1,7 @@ +#ifdef WHAL_CFG_STM32U5_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32U5_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE +#endif +#include "stm32wb_uart.c" diff --git a/src/uart/stm32wb_uart.c b/src/uart/stm32wb_uart.c index 6f3bcba..1086ecc 100644 --- a/src/uart/stm32wb_uart.c +++ b/src/uart/stm32wb_uart.c @@ -20,11 +20,7 @@ */ #include -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE #include "board.h" /* provides whal_Stm32wb_Uart_Dev singleton (possibly via platform alias macro) */ #endif #include @@ -69,11 +65,7 @@ #define UART_TDR_Pos 0 #define UART_TDR_Msk (WHAL_BITMASK(9) << UART_TDR_Pos) -#if defined(WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32H5_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32C0_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_UART_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32WBA_UART_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING #define whal_Stm32wb_Uart_Init whal_Uart_Init #define whal_Stm32wb_Uart_Deinit whal_Uart_Deinit #define whal_Stm32wb_Uart_Send whal_Uart_Send @@ -87,22 +79,14 @@ #define whal_Stm32wb_Uart_Deinit whal_Uart_Deinit #endif /* WHAL_CFG_STM32WB_UART_DMA_DIRECT_API_MAPPING */ -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Uart whal_Stm32wb_Uart_Dev = WHAL_CFG_STM32WB_UART_DEV; #endif whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) { uint32_t brr; -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; size_t base = whal_Stm32wb_Uart_Dev.base; @@ -137,11 +121,7 @@ whal_Error whal_Stm32wb_Uart_Init(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) { -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE size_t base = whal_Stm32wb_Uart_Dev.base; (void)uartDev; #else @@ -170,11 +150,7 @@ whal_Error whal_Stm32wb_Uart_Deinit(whal_Uart *uartDev) whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t dataSz) { const uint8_t *buf = data; -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; size_t base = whal_Stm32wb_Uart_Dev.base; @@ -212,11 +188,7 @@ whal_Error whal_Stm32wb_Uart_Send(whal_Uart *uartDev, const void *data, size_t d whal_Error whal_Stm32wb_Uart_Recv(whal_Uart *uartDev, void *data, size_t dataSz) { uint8_t *buf = data; -#if defined(WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32H5_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32C0_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32N6_UART_SINGLE_INSTANCE) || \ - defined(WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE) +#ifdef WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE const whal_Stm32wb_Uart_Cfg *cfg = (const whal_Stm32wb_Uart_Cfg *)whal_Stm32wb_Uart_Dev.cfg; size_t base = whal_Stm32wb_Uart_Dev.base; @@ -271,11 +243,7 @@ whal_Error whal_Stm32wb_Uart_RecvAsync(whal_Uart *uartDev, void *data, size_t da } #if !defined(WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32WB_UART_DMA_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32H5_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32C0_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_UART_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32WBA_UART_DIRECT_API_MAPPING) + !defined(WHAL_CFG_STM32WB_UART_DMA_DIRECT_API_MAPPING) const whal_UartDriver whal_Stm32wb_Uart_Driver = { .Init = whal_Stm32wb_Uart_Init, .Deinit = whal_Stm32wb_Uart_Deinit, diff --git a/src/uart/stm32wba_uart.c b/src/uart/stm32wba_uart.c index 5c08ad7..5ba7750 100644 --- a/src/uart/stm32wba_uart.c +++ b/src/uart/stm32wba_uart.c @@ -19,4 +19,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32WBA_UART_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_UART_DIRECT_API_MAPPING +#endif +#ifdef WHAL_CFG_STM32WBA_UART_SINGLE_INSTANCE +#define WHAL_CFG_STM32WB_UART_SINGLE_INSTANCE +#endif #include "stm32wb_uart.c" diff --git a/src/watchdog/stm32f0_iwdg.c b/src/watchdog/stm32f0_iwdg.c index 979f60f..b3dbb84 100644 --- a/src/watchdog/stm32f0_iwdg.c +++ b/src/watchdog/stm32f0_iwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F0_IWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING +#endif #include "stm32wb_iwdg.c" diff --git a/src/watchdog/stm32f0_wwdg.c b/src/watchdog/stm32f0_wwdg.c index 53241eb..3da10d1 100644 --- a/src/watchdog/stm32f0_wwdg.c +++ b/src/watchdog/stm32f0_wwdg.c @@ -42,9 +42,7 @@ const whal_Watchdog whal_Stm32f0_Wwdg_Dev = WHAL_CFG_STM32F0_WWDG_DEV; #define CFR_EWI_Pos 9 #define CFR_EWI_Msk (1UL << CFR_EWI_Pos) -#if defined(WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_WWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32L1_WWDG_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING #define whal_Stm32f0_Wwdg_Init whal_Watchdog_Init #define whal_Stm32f0_Wwdg_Deinit whal_Watchdog_Deinit #define whal_Stm32f0_Wwdg_Refresh whal_Watchdog_Refresh @@ -87,9 +85,7 @@ whal_Error whal_Stm32f0_Wwdg_Refresh(whal_Watchdog *wdgDev) return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_WWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32L1_WWDG_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING const whal_WatchdogDriver whal_Stm32f0_Wwdg_Driver = { .Init = whal_Stm32f0_Wwdg_Init, .Deinit = whal_Stm32f0_Wwdg_Deinit, diff --git a/src/watchdog/stm32f3_iwdg.c b/src/watchdog/stm32f3_iwdg.c index 6f0ce50..8bca17d 100644 --- a/src/watchdog/stm32f3_iwdg.c +++ b/src/watchdog/stm32f3_iwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_IWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING +#endif #include "stm32wb_iwdg.c" diff --git a/src/watchdog/stm32f3_wwdg.c b/src/watchdog/stm32f3_wwdg.c index 5c443bd..5333e85 100644 --- a/src/watchdog/stm32f3_wwdg.c +++ b/src/watchdog/stm32f3_wwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32F3_WWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING +#endif #include "stm32f0_wwdg.c" diff --git a/src/watchdog/stm32l1_iwdg.c b/src/watchdog/stm32l1_iwdg.c index ceb3529..775519a 100644 --- a/src/watchdog/stm32l1_iwdg.c +++ b/src/watchdog/stm32l1_iwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32L1_IWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING +#endif #include "stm32wb_iwdg.c" diff --git a/src/watchdog/stm32l1_wwdg.c b/src/watchdog/stm32l1_wwdg.c index b45244c..77585e5 100644 --- a/src/watchdog/stm32l1_wwdg.c +++ b/src/watchdog/stm32l1_wwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32L1_WWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32F0_WWDG_DIRECT_API_MAPPING +#endif #include "stm32f0_wwdg.c" diff --git a/src/watchdog/stm32n6_iwdg.c b/src/watchdog/stm32n6_iwdg.c index 7d01183..25e12eb 100644 --- a/src/watchdog/stm32n6_iwdg.c +++ b/src/watchdog/stm32n6_iwdg.c @@ -19,4 +19,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA */ +#ifdef WHAL_CFG_STM32N6_IWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING +#endif #include "stm32wb_iwdg.c" diff --git a/src/watchdog/stm32u5_iwdg.c b/src/watchdog/stm32u5_iwdg.c new file mode 100644 index 0000000..dd6ae39 --- /dev/null +++ b/src/watchdog/stm32u5_iwdg.c @@ -0,0 +1,4 @@ +#ifdef WHAL_CFG_STM32U5_IWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING +#endif +#include "stm32wb_iwdg.c" diff --git a/src/watchdog/stm32u5_wwdg.c b/src/watchdog/stm32u5_wwdg.c new file mode 100644 index 0000000..86a6444 --- /dev/null +++ b/src/watchdog/stm32u5_wwdg.c @@ -0,0 +1,4 @@ +#ifdef WHAL_CFG_STM32U5_WWDG_DIRECT_API_MAPPING +#define WHAL_CFG_STM32WB_WWDG_DIRECT_API_MAPPING +#endif +#include "stm32wb_wwdg.c" diff --git a/src/watchdog/stm32wb_iwdg.c b/src/watchdog/stm32wb_iwdg.c index 9e27414..01a1f89 100644 --- a/src/watchdog/stm32wb_iwdg.c +++ b/src/watchdog/stm32wb_iwdg.c @@ -58,11 +58,7 @@ const whal_Watchdog whal_Stm32wb_Iwdg_Dev = WHAL_CFG_STM32WB_IWDG_DEV; #define IWDG_SR_RVU_Pos 1 /* Reload value update */ #define IWDG_SR_RVU_Msk (1UL << IWDG_SR_RVU_Pos) -#if defined(WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F0_IWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32F3_IWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32L1_IWDG_DIRECT_API_MAPPING) || \ - defined(WHAL_CFG_STM32N6_IWDG_DIRECT_API_MAPPING) +#ifdef WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING #define whal_Stm32wb_Iwdg_Init whal_Watchdog_Init #define whal_Stm32wb_Iwdg_Deinit whal_Watchdog_Deinit #define whal_Stm32wb_Iwdg_Refresh whal_Watchdog_Refresh @@ -119,11 +115,7 @@ whal_Error whal_Stm32wb_Iwdg_Refresh(whal_Watchdog *wdgDev) return WHAL_SUCCESS; } -#if !defined(WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F0_IWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32F3_IWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32L1_IWDG_DIRECT_API_MAPPING) && \ - !defined(WHAL_CFG_STM32N6_IWDG_DIRECT_API_MAPPING) +#ifndef WHAL_CFG_STM32WB_IWDG_DIRECT_API_MAPPING const whal_WatchdogDriver whal_Stm32wb_Iwdg_Driver = { .Init = whal_Stm32wb_Iwdg_Init, .Deinit = whal_Stm32wb_Iwdg_Deinit, diff --git a/tests/flash/test_flash.c b/tests/flash/test_flash.c index f5c6990..ef96fd1 100644 --- a/tests/flash/test_flash.c +++ b/tests/flash/test_flash.c @@ -49,12 +49,13 @@ static void Test_Flash_WriteReadErase(void) WHAL_ASSERT_EQ(whal_Flash_Unlock(g_testFlashDev, g_testFlashAddr, g_testFlashSectorSz), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Flash_Erase(g_testFlashDev, g_testFlashAddr, + g_testFlashSectorSz), WHAL_SUCCESS); + WHAL_ASSERT_EQ(whal_Flash_Read(g_testFlashDev, g_testFlashAddr, readback, sizeof(readback)), WHAL_SUCCESS); WHAL_ASSERT_MEM_NEQ(readback, pattern, sizeof(pattern)); - WHAL_ASSERT_EQ(whal_Flash_Erase(g_testFlashDev, g_testFlashAddr, - g_testFlashSectorSz), WHAL_SUCCESS); do { err = whal_Flash_Write(g_testFlashDev, g_testFlashAddr, pattern, diff --git a/wolfHAL/clock/stm32u5_rcc.h b/wolfHAL/clock/stm32u5_rcc.h new file mode 100644 index 0000000..91af502 --- /dev/null +++ b/wolfHAL/clock/stm32u5_rcc.h @@ -0,0 +1,436 @@ +/* stm32u5_rcc.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_RCC_H +#define WHAL_STM32U5_RCC_H + +#include +#include +#include +#include +#include + +/** + * @file stm32u5_rcc.h + * @brief STM32U5 RCC (Reset and Clock Control) driver. + * + * Boards bring up the clock tree imperatively from Board_Init. The RCC + * peripheral lives at a fixed address — clock is a board-level driver + * with no device struct, no generic API, no vtable. + * + * Differences from STM32WBA: + * - PLL1M is 4 bits (bits 11:8) — selects /1 to /16 + * - PLL1CFGR adds PLL1MBOOST (bits 15:12) and PLL1FRACEN (bit 4) + * - Voltage scaling has four ranges (VOS[1:0]: 0=Range 4, 1=Range 3, + * 2=Range 2, 3=Range 1). EPOD booster must be enabled for SYSCLK + * above 55 MHz in Range 1. + * - MSI oscillator available (MSIS for sysclk, MSIK for kernel). + */ + +#define WHAL_STM32U5_RCC_BASE 0x46020C00 + +#define WHAL_STM32U5_RCC_CR_REG 0x000 +#define WHAL_STM32U5_RCC_CR_MSISON_Msk (1UL << 0) +#define WHAL_STM32U5_RCC_CR_MSISRDY_Msk (1UL << 2) +#define WHAL_STM32U5_RCC_CR_MSISRDY_Pos 2 +#define WHAL_STM32U5_RCC_CR_HSION_Msk (1UL << 8) +#define WHAL_STM32U5_RCC_CR_HSIRDY_Msk (1UL << 10) +#define WHAL_STM32U5_RCC_CR_HSIRDY_Pos 10 +#define WHAL_STM32U5_RCC_CR_HSEON_Msk (1UL << 16) +#define WHAL_STM32U5_RCC_CR_HSERDY_Msk (1UL << 17) +#define WHAL_STM32U5_RCC_CR_HSERDY_Pos 17 +#define WHAL_STM32U5_RCC_CR_PLL1ON_Msk (1UL << 24) +#define WHAL_STM32U5_RCC_CR_PLL1RDY_Msk (1UL << 25) +#define WHAL_STM32U5_RCC_CR_PLL1RDY_Pos 25 + +#define WHAL_STM32U5_RCC_CFGR1_REG 0x01C +#define WHAL_STM32U5_RCC_CFGR1_SW_Pos 0 +#define WHAL_STM32U5_RCC_CFGR1_SW_Msk (3UL << WHAL_STM32U5_RCC_CFGR1_SW_Pos) +#define WHAL_STM32U5_RCC_CFGR1_SWS_Pos 2 +#define WHAL_STM32U5_RCC_CFGR1_SWS_Msk (3UL << WHAL_STM32U5_RCC_CFGR1_SWS_Pos) + +/* PLL1CFGR bit layout differs from WBA: PLL1M is 4 bits wide, + * PLL1MBOOST sits at 15:12, PLL1FRACEN at bit 4. */ +#define WHAL_STM32U5_RCC_PLL1CFGR_REG 0x028 +#define WHAL_STM32U5_RCC_PLL1CFGR_SRC_Pos 0 +#define WHAL_STM32U5_RCC_PLL1CFGR_SRC_Msk (3UL << WHAL_STM32U5_RCC_PLL1CFGR_SRC_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_RGE_Pos 2 +#define WHAL_STM32U5_RCC_PLL1CFGR_RGE_Msk (3UL << WHAL_STM32U5_RCC_PLL1CFGR_RGE_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_FRACEN_Pos 4 +#define WHAL_STM32U5_RCC_PLL1CFGR_FRACEN_Msk (1UL << WHAL_STM32U5_RCC_PLL1CFGR_FRACEN_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_M_Pos 8 +#define WHAL_STM32U5_RCC_PLL1CFGR_M_Msk (0xFUL << WHAL_STM32U5_RCC_PLL1CFGR_M_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Pos 12 +#define WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Msk (0xFUL << WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_PEN_Pos 16 +#define WHAL_STM32U5_RCC_PLL1CFGR_PEN_Msk (1UL << WHAL_STM32U5_RCC_PLL1CFGR_PEN_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_QEN_Pos 17 +#define WHAL_STM32U5_RCC_PLL1CFGR_QEN_Msk (1UL << WHAL_STM32U5_RCC_PLL1CFGR_QEN_Pos) +#define WHAL_STM32U5_RCC_PLL1CFGR_REN_Pos 18 +#define WHAL_STM32U5_RCC_PLL1CFGR_REN_Msk (1UL << WHAL_STM32U5_RCC_PLL1CFGR_REN_Pos) + +#define WHAL_STM32U5_RCC_PLL1DIVR_REG 0x034 +#define WHAL_STM32U5_RCC_PLL1DIVR_N_Pos 0 +#define WHAL_STM32U5_RCC_PLL1DIVR_N_Msk (0x1FFUL << WHAL_STM32U5_RCC_PLL1DIVR_N_Pos) +#define WHAL_STM32U5_RCC_PLL1DIVR_P_Pos 9 +#define WHAL_STM32U5_RCC_PLL1DIVR_P_Msk (0x7FUL << WHAL_STM32U5_RCC_PLL1DIVR_P_Pos) +#define WHAL_STM32U5_RCC_PLL1DIVR_Q_Pos 16 +#define WHAL_STM32U5_RCC_PLL1DIVR_Q_Msk (0x7FUL << WHAL_STM32U5_RCC_PLL1DIVR_Q_Pos) +#define WHAL_STM32U5_RCC_PLL1DIVR_R_Pos 24 +#define WHAL_STM32U5_RCC_PLL1DIVR_R_Msk (0x7FUL << WHAL_STM32U5_RCC_PLL1DIVR_R_Pos) + +/* BDCR1 holds LSE/LSI/RTC clocking */ +#define WHAL_STM32U5_RCC_BDCR_REG 0x0F0 +#define WHAL_STM32U5_RCC_BDCR_LSION_Msk (1UL << 26) +#define WHAL_STM32U5_RCC_BDCR_LSIRDY_Msk (1UL << 27) +#define WHAL_STM32U5_RCC_BDCR_LSIRDY_Pos 27 + +#define WHAL_STM32U5_RCC_CCIPR2_REG 0x0E4 +#define WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Pos 12 +#define WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk (3UL << WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Pos) + +/* PWR registers used during clock bring-up */ +#define WHAL_STM32U5_PWR_BASE 0x46020800 +#define WHAL_STM32U5_PWR_VOSR_REG 0x00C +#define WHAL_STM32U5_PWR_VOSR_VOSRDY_Msk (1UL << 15) +#define WHAL_STM32U5_PWR_VOSR_VOSRDY_Pos 15 +#define WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Msk (1UL << 14) +#define WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Pos 14 +#define WHAL_STM32U5_PWR_VOSR_VOS_Pos 16 +#define WHAL_STM32U5_PWR_VOSR_VOS_Msk (3UL << WHAL_STM32U5_PWR_VOSR_VOS_Pos) +#define WHAL_STM32U5_PWR_VOSR_BOOSTEN_Pos 18 +#define WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk (1UL << 18) + +/** + * @brief System clock source selection (RCC_CFGR1.SW). + */ +typedef enum { + WHAL_STM32U5_RCC_SYSCLK_SRC_MSIS = 0, + WHAL_STM32U5_RCC_SYSCLK_SRC_HSI16 = 1, + WHAL_STM32U5_RCC_SYSCLK_SRC_HSE = 2, + WHAL_STM32U5_RCC_SYSCLK_SRC_PLL1 = 3, +} whal_Stm32u5_Rcc_SysClockSrc; + +/** + * @brief PLL1 input clock source selection. + */ +typedef enum { + WHAL_STM32U5_RCC_PLL1SRC_NONE = 0, + WHAL_STM32U5_RCC_PLL1SRC_MSIS = 1, + WHAL_STM32U5_RCC_PLL1SRC_HSI16 = 2, + WHAL_STM32U5_RCC_PLL1SRC_HSE = 3, +} whal_Stm32u5_Rcc_Pll1Src; + +/** + * @brief PLL1 input reference frequency range. + */ +typedef enum { + WHAL_STM32U5_RCC_PLL1RGE_4_8 = 0, + WHAL_STM32U5_RCC_PLL1RGE_8_16 = 3, +} whal_Stm32u5_Rcc_Pll1Rge; + +/** + * @brief Voltage scaling range (PWR_VOSR.VOS[1:0]). Range 1 is required for + * SYSCLK above 24 MHz; the EPOD booster is required above 55 MHz. + */ +typedef enum { + WHAL_STM32U5_PWR_VOS_RANGE_4 = 0, + WHAL_STM32U5_PWR_VOS_RANGE_3 = 1, + WHAL_STM32U5_PWR_VOS_RANGE_2 = 2, + WHAL_STM32U5_PWR_VOS_RANGE_1 = 3, +} whal_Stm32u5_Pwr_VosRange; + +/** + * @brief PLL1 configuration parameters. + * f_ref = f_input / m [4-16 MHz] + * f_vco = f_ref * n [128-544 MHz] + * f_pll1r = f_vco / r [SYSCLK output, max 160 MHz] + * + * `m`, `n`, `r`, `q`, `p` are the actual divider/multiplier values; the + * driver encodes them as field = value - 1 when writing the register + * (matching ST HAL conventions). Valid ranges: m=1..16, n=4..512, + * r/q/p=1..128. + * + * `mboost` is the EPOD prescaler field — written raw; 0 bypasses the + * prescaler. + */ +typedef struct { + whal_Stm32u5_Rcc_Pll1Src clkSrc; + whal_Stm32u5_Rcc_Pll1Rge rge; + uint8_t m; /**< PLL1M divider, 1..16 */ + uint8_t mboost; /**< PLL1MBOOST[3:0] — 0 bypasses EPOD prescaler */ + uint16_t n; /**< PLL1N multiplier, 4..512 */ + uint8_t r; /**< PLL1R divider, 1..128 (SYSCLK output) */ + uint8_t q; /**< PLL1Q divider, 1..128 */ + uint8_t p; /**< PLL1P divider, 1..128 */ +} whal_Stm32u5_Rcc_Pll1Cfg; + +/** + * @brief RNG kernel clock source selection (RCC_CCIPR2.RNGSEL). + */ +typedef enum { + WHAL_STM32U5_RCC_RNGSEL_HSI48 = 0, + WHAL_STM32U5_RCC_RNGSEL_HSI48_DIV2 = 1, + WHAL_STM32U5_RCC_RNGSEL_HSI16 = 2, +} whal_Stm32u5_Rcc_RngSrc; + +/** + * @brief Peripheral clock descriptor. + */ +typedef struct { + size_t regOffset; + size_t enableMask; + size_t enablePos; +} whal_Stm32u5_Rcc_PeriphClk; + +/** + * @brief Cfg for EnableOsc/DisableOsc — on bit + ready bit. + */ +typedef struct { + size_t onReg; + size_t onMsk; + size_t rdyReg; + size_t rdyMsk; + size_t rdyPos; +} whal_Stm32u5_Rcc_OscCfg; + +#define WHAL_STM32U5_RCC_HSI16_CFG \ + .onReg = 0x000, .onMsk = (1UL << 8), \ + .rdyReg = 0x000, .rdyMsk = (1UL << 10), .rdyPos = 10 +#define WHAL_STM32U5_RCC_HSE_CFG \ + .onReg = 0x000, .onMsk = (1UL << 16), \ + .rdyReg = 0x000, .rdyMsk = (1UL << 17), .rdyPos = 17 + +/** + * @brief Turn on an oscillator (HSI16/HSE) and wait for its ready bit. + * + * @param cfg Oscillator on/ready bit descriptor. + */ +static inline whal_Error whal_Stm32u5_Rcc_EnableOsc( + const whal_Stm32u5_Rcc_OscCfg *cfg) +{ + size_t rdy; + + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, cfg->onMsk); + do { + whal_Reg_Get(WHAL_STM32U5_RCC_BASE, cfg->rdyReg, cfg->rdyMsk, + cfg->rdyPos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +/** + * @brief Turn off an oscillator. + */ +static inline whal_Error whal_Stm32u5_Rcc_DisableOsc( + const whal_Stm32u5_Rcc_OscCfg *cfg) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, cfg->onReg, cfg->onMsk, 0); + return WHAL_SUCCESS; +} + +/** + * @brief Configure and enable PLL1, waiting for lock. + */ +static inline whal_Error whal_Stm32u5_Rcc_EnablePll1( + const whal_Stm32u5_Rcc_Pll1Cfg *cfg) +{ + size_t rdy; + + /* Disable PLL1 before reconfiguring; wait until off. */ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); + do { + whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); + } while (rdy); + + whal_Reg_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1CFGR_REG, + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_SRC_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_SRC_Pos, cfg->clkSrc) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_RGE_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_RGE_Pos, cfg->rge) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_M_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_M_Pos, cfg->m - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_MBOOST_Pos, + cfg->mboost) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1CFGR_REN_Msk, + WHAL_STM32U5_RCC_PLL1CFGR_REN_Pos, 1)); + whal_Reg_Write(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_PLL1DIVR_REG, + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_N_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_N_Pos, cfg->n - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_P_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_P_Pos, cfg->p - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_Q_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_Q_Pos, cfg->q - 1) | + whal_SetBits(WHAL_STM32U5_RCC_PLL1DIVR_R_Msk, + WHAL_STM32U5_RCC_PLL1DIVR_R_Pos, cfg->r - 1)); + + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk); + do { + whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1RDY_Msk, + WHAL_STM32U5_RCC_CR_PLL1RDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +/** + * @brief Turn PLL1 off (clears RCC_CR.PLL1ON). + */ +static inline whal_Error whal_Stm32u5_Rcc_DisablePll1(void) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CR_REG, + WHAL_STM32U5_RCC_CR_PLL1ON_Msk, 0); + return WHAL_SUCCESS; +} + +/** + * @brief Enable LSI (32 kHz internal RC) and wait for ready. + */ +static inline whal_Error whal_Stm32u5_Rcc_EnableLsi(void) +{ + size_t rdy; + + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSION_Msk, + WHAL_STM32U5_RCC_BDCR_LSION_Msk); + do { + whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSIRDY_Msk, + WHAL_STM32U5_RCC_BDCR_LSIRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +/** + * @brief Disable LSI. + */ +static inline whal_Error whal_Stm32u5_Rcc_DisableLsi(void) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_BDCR_REG, + WHAL_STM32U5_RCC_BDCR_LSION_Msk, 0); + return WHAL_SUCCESS; +} + +/** + * @brief Switch SYSCLK to the requested source and wait for the switch. + */ +static inline whal_Error whal_Stm32u5_Rcc_SetSysClock( + whal_Stm32u5_Rcc_SysClockSrc src) +{ + size_t sws; + + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, + WHAL_STM32U5_RCC_CFGR1_SW_Msk, + whal_SetBits(WHAL_STM32U5_RCC_CFGR1_SW_Msk, + WHAL_STM32U5_RCC_CFGR1_SW_Pos, src)); + do { + whal_Reg_Get(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CFGR1_REG, + WHAL_STM32U5_RCC_CFGR1_SWS_Msk, + WHAL_STM32U5_RCC_CFGR1_SWS_Pos, &sws); + } while (sws != (size_t)src); + return WHAL_SUCCESS; +} + +/** + * @brief Select the RNG kernel clock source (RCC_CCIPR2.RNGSEL). + */ +static inline whal_Error whal_Stm32u5_Rcc_SetRngClockSrc( + whal_Stm32u5_Rcc_RngSrc src) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, WHAL_STM32U5_RCC_CCIPR2_REG, + WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, + whal_SetBits(WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Msk, + WHAL_STM32U5_RCC_CCIPR2_RNGSEL_Pos, + src)); + return WHAL_SUCCESS; +} + +/** + * @brief Set the enable bit for a peripheral clock gate. + */ +static inline whal_Error whal_Stm32u5_Rcc_EnablePeriphClk( + const whal_Stm32u5_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 1)); + return WHAL_SUCCESS; +} + +/** + * @brief Clear the enable bit for a peripheral clock gate. + */ +static inline whal_Error whal_Stm32u5_Rcc_DisablePeriphClk( + const whal_Stm32u5_Rcc_PeriphClk *clk) +{ + whal_Reg_Update(WHAL_STM32U5_RCC_BASE, clk->regOffset, clk->enableMask, + whal_SetBits(clk->enableMask, clk->enablePos, 0)); + return WHAL_SUCCESS; +} + +/** + * @brief Program the PWR voltage scaling range and wait for VOSRDY. + * VOS Range 1 is required before SYSCLK exceeds 24 MHz; the EPOD + * booster (BOOSTEN) is required for SYSCLK above 55 MHz. + */ +static inline whal_Error whal_Stm32u5_Pwr_SetVosRange( + whal_Stm32u5_Pwr_VosRange range) +{ + size_t rdy; + + whal_Reg_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_VOS_Msk, + whal_SetBits(WHAL_STM32U5_PWR_VOSR_VOS_Msk, + WHAL_STM32U5_PWR_VOSR_VOS_Pos, range)); + do { + whal_Reg_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_VOSRDY_Msk, + WHAL_STM32U5_PWR_VOSR_VOSRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +/** + * @brief Enable the EPOD booster (PWR_VOSR.BOOSTEN) and wait for BOOSTRDY. + * Required for SYSCLK above 55 MHz on Range 1. + */ +static inline whal_Error whal_Stm32u5_Pwr_EnableEpodBooster(void) +{ + size_t rdy; + + whal_Reg_Update(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, + whal_SetBits(WHAL_STM32U5_PWR_VOSR_BOOSTEN_Msk, + WHAL_STM32U5_PWR_VOSR_BOOSTEN_Pos, 1)); + do { + whal_Reg_Get(WHAL_STM32U5_PWR_BASE, WHAL_STM32U5_PWR_VOSR_REG, + WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Msk, + WHAL_STM32U5_PWR_VOSR_BOOSTRDY_Pos, &rdy); + } while (!rdy); + return WHAL_SUCCESS; +} + +#endif /* WHAL_STM32U5_RCC_H */ diff --git a/wolfHAL/crypto/stm32n6_hash.h b/wolfHAL/crypto/stm32n6_hash.h index 623bac0..34e2850 100644 --- a/wolfHAL/crypto/stm32n6_hash.h +++ b/wolfHAL/crypto/stm32n6_hash.h @@ -56,4 +56,14 @@ typedef whal_Stm32wba_HmacSha256_State whal_Stm32n6_HmacSha256_State; #define whal_Stm32n6_Hash_HmacSha224Driver whal_Stm32wba_Hash_HmacSha224Driver #define whal_Stm32n6_Hash_HmacSha256Driver whal_Stm32wba_Hash_HmacSha256Driver +/* Config initializer macro aliases. The N6 board.h supplies the bodies + * under N6-prefixed names; the WBA driver source consumes the WBA names. */ +#define WHAL_CFG_STM32WBA_HASH_DEV WHAL_CFG_STM32N6_HASH_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA1_DEV WHAL_CFG_STM32N6_HASH_SHA1_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA224_DEV WHAL_CFG_STM32N6_HASH_SHA224_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA256_DEV WHAL_CFG_STM32N6_HASH_SHA256_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DEV WHAL_CFG_STM32N6_HASH_HMAC_SHA1_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DEV WHAL_CFG_STM32N6_HASH_HMAC_SHA224_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DEV WHAL_CFG_STM32N6_HASH_HMAC_SHA256_DEV + #endif /* WHAL_STM32N6_HASH_H */ diff --git a/wolfHAL/crypto/stm32u5_aes.h b/wolfHAL/crypto/stm32u5_aes.h new file mode 100644 index 0000000..145f914 --- /dev/null +++ b/wolfHAL/crypto/stm32u5_aes.h @@ -0,0 +1,68 @@ +/* stm32u5_aes.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_AES_H +#define WHAL_STM32U5_AES_H + +/** + * @file stm32u5_aes.h + * @brief STM32U5 AES driver (alias for STM32WB AES). + * + * The STM32U5 AES peripheral is register-compatible with the STM32WB AES. + * This header re-exports the STM32WB AES driver types and symbols under + * STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wb_Aes_Cfg whal_Stm32u5_Aes_Cfg; + +typedef whal_Stm32wb_AesGcm_State whal_Stm32u5_AesGcm_State; +typedef whal_Stm32wb_AesCcm_State whal_Stm32u5_AesCcm_State; + +#define whal_Stm32u5_Aes_Dev whal_Stm32wb_Aes_Dev +#define whal_Stm32u5_AesEcb_Dev whal_Stm32wb_AesEcb_Dev +#define whal_Stm32u5_AesCbc_Dev whal_Stm32wb_AesCbc_Dev +#define whal_Stm32u5_AesCtr_Dev whal_Stm32wb_AesCtr_Dev +#define whal_Stm32u5_AesGcm_Dev whal_Stm32wb_AesGcm_Dev +#define whal_Stm32u5_AesGmac_Dev whal_Stm32wb_AesGmac_Dev +#define whal_Stm32u5_AesCcm_Dev whal_Stm32wb_AesCcm_Dev + +#define whal_Stm32u5_Aes_CryptoDriver whal_Stm32wb_Aes_CryptoDriver + +#define whal_Stm32u5_Aes_EcbDriver whal_Stm32wb_Aes_EcbDriver +#define whal_Stm32u5_Aes_CbcDriver whal_Stm32wb_Aes_CbcDriver +#define whal_Stm32u5_Aes_CtrDriver whal_Stm32wb_Aes_CtrDriver +#define whal_Stm32u5_Aes_GcmDriver whal_Stm32wb_Aes_GcmDriver +#define whal_Stm32u5_Aes_GmacDriver whal_Stm32wb_Aes_GmacDriver +#define whal_Stm32u5_Aes_CcmDriver whal_Stm32wb_Aes_CcmDriver + +/* Config initializer macro aliases. The U5 board.h supplies the bodies + * under U5-prefixed names; the WB driver source consumes the WB names. */ +#define WHAL_CFG_STM32WB_AES_DEV WHAL_CFG_STM32U5_AES_DEV +#define WHAL_CFG_STM32WB_AES_ECB_DEV WHAL_CFG_STM32U5_AES_ECB_DEV +#define WHAL_CFG_STM32WB_AES_CBC_DEV WHAL_CFG_STM32U5_AES_CBC_DEV +#define WHAL_CFG_STM32WB_AES_CTR_DEV WHAL_CFG_STM32U5_AES_CTR_DEV +#define WHAL_CFG_STM32WB_AES_GCM_DEV WHAL_CFG_STM32U5_AES_GCM_DEV +#define WHAL_CFG_STM32WB_AES_GMAC_DEV WHAL_CFG_STM32U5_AES_GMAC_DEV +#define WHAL_CFG_STM32WB_AES_CCM_DEV WHAL_CFG_STM32U5_AES_CCM_DEV + +#endif /* WHAL_STM32U5_AES_H */ diff --git a/wolfHAL/crypto/stm32u5_hash.h b/wolfHAL/crypto/stm32u5_hash.h new file mode 100644 index 0000000..2032732 --- /dev/null +++ b/wolfHAL/crypto/stm32u5_hash.h @@ -0,0 +1,104 @@ +/* stm32u5_hash.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_HASH_H +#define WHAL_STM32U5_HASH_H + +/** + * @file stm32u5_hash.h + * @brief STM32U5 HASH driver (alias for STM32WBA HASH). + * + * The STM32U5 HASH peripheral is register-compatible with the STM32WBA HASH. + * This header re-exports the STM32WBA HASH driver types and symbols under + * STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wba_Hash_Cfg whal_Stm32u5_Hash_Cfg; + +typedef whal_Stm32wba_HmacSha1_State whal_Stm32u5_HmacSha1_State; +typedef whal_Stm32wba_HmacSha224_State whal_Stm32u5_HmacSha224_State; +typedef whal_Stm32wba_HmacSha256_State whal_Stm32u5_HmacSha256_State; + +/* Singleton aliases */ +#define whal_Stm32u5_Hash_Dev whal_Stm32wba_Hash_Dev +#define whal_Stm32u5_Sha1_Dev whal_Stm32wba_Sha1_Dev +#define whal_Stm32u5_Sha224_Dev whal_Stm32wba_Sha224_Dev +#define whal_Stm32u5_Sha256_Dev whal_Stm32wba_Sha256_Dev +#define whal_Stm32u5_HmacSha1_Dev whal_Stm32wba_HmacSha1_Dev +#define whal_Stm32u5_HmacSha224_Dev whal_Stm32wba_HmacSha224_Dev +#define whal_Stm32u5_HmacSha256_Dev whal_Stm32wba_HmacSha256_Dev + +/* Vtable aliases */ +#define whal_Stm32u5_Hash_CryptoDriver whal_Stm32wba_Hash_CryptoDriver +#define whal_Stm32u5_Hash_Sha1Driver whal_Stm32wba_Hash_Sha1Driver +#define whal_Stm32u5_Hash_Sha224Driver whal_Stm32wba_Hash_Sha224Driver +#define whal_Stm32u5_Hash_Sha256Driver whal_Stm32wba_Hash_Sha256Driver +#define whal_Stm32u5_Hash_HmacSha1Driver whal_Stm32wba_Hash_HmacSha1Driver +#define whal_Stm32u5_Hash_HmacSha224Driver whal_Stm32wba_Hash_HmacSha224Driver +#define whal_Stm32u5_Hash_HmacSha256Driver whal_Stm32wba_Hash_HmacSha256Driver + +/* Function aliases */ +#define whal_Stm32u5_Hash_Init whal_Stm32wba_Hash_Init +#define whal_Stm32u5_Hash_Deinit whal_Stm32wba_Hash_Deinit + +#define whal_Stm32u5_Sha1_Oneshot whal_Stm32wba_Sha1_Oneshot +#define whal_Stm32u5_Sha1_Start whal_Stm32wba_Sha1_Start +#define whal_Stm32u5_Sha1_Process whal_Stm32wba_Sha1_Process +#define whal_Stm32u5_Sha1_Finalize whal_Stm32wba_Sha1_Finalize + +#define whal_Stm32u5_Sha224_Oneshot whal_Stm32wba_Sha224_Oneshot +#define whal_Stm32u5_Sha224_Start whal_Stm32wba_Sha224_Start +#define whal_Stm32u5_Sha224_Process whal_Stm32wba_Sha224_Process +#define whal_Stm32u5_Sha224_Finalize whal_Stm32wba_Sha224_Finalize + +#define whal_Stm32u5_Sha256_Oneshot whal_Stm32wba_Sha256_Oneshot +#define whal_Stm32u5_Sha256_Start whal_Stm32wba_Sha256_Start +#define whal_Stm32u5_Sha256_Process whal_Stm32wba_Sha256_Process +#define whal_Stm32u5_Sha256_Finalize whal_Stm32wba_Sha256_Finalize + +#define whal_Stm32u5_HmacSha1_Oneshot whal_Stm32wba_HmacSha1_Oneshot +#define whal_Stm32u5_HmacSha1_Start whal_Stm32wba_HmacSha1_Start +#define whal_Stm32u5_HmacSha1_Process whal_Stm32wba_HmacSha1_Process +#define whal_Stm32u5_HmacSha1_Finalize whal_Stm32wba_HmacSha1_Finalize + +#define whal_Stm32u5_HmacSha224_Oneshot whal_Stm32wba_HmacSha224_Oneshot +#define whal_Stm32u5_HmacSha224_Start whal_Stm32wba_HmacSha224_Start +#define whal_Stm32u5_HmacSha224_Process whal_Stm32wba_HmacSha224_Process +#define whal_Stm32u5_HmacSha224_Finalize whal_Stm32wba_HmacSha224_Finalize + +#define whal_Stm32u5_HmacSha256_Oneshot whal_Stm32wba_HmacSha256_Oneshot +#define whal_Stm32u5_HmacSha256_Start whal_Stm32wba_HmacSha256_Start +#define whal_Stm32u5_HmacSha256_Process whal_Stm32wba_HmacSha256_Process +#define whal_Stm32u5_HmacSha256_Finalize whal_Stm32wba_HmacSha256_Finalize + +/* Config initializer macro aliases. The U5 board.h supplies the bodies + * under U5-prefixed names; the WBA driver source consumes the WBA names. */ +#define WHAL_CFG_STM32WBA_HASH_DEV WHAL_CFG_STM32U5_HASH_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA1_DEV WHAL_CFG_STM32U5_HASH_SHA1_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA224_DEV WHAL_CFG_STM32U5_HASH_SHA224_DEV +#define WHAL_CFG_STM32WBA_HASH_SHA256_DEV WHAL_CFG_STM32U5_HASH_SHA256_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA1_DEV WHAL_CFG_STM32U5_HASH_HMAC_SHA1_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA224_DEV WHAL_CFG_STM32U5_HASH_HMAC_SHA224_DEV +#define WHAL_CFG_STM32WBA_HASH_HMAC_SHA256_DEV WHAL_CFG_STM32U5_HASH_HMAC_SHA256_DEV + +#endif /* WHAL_STM32U5_HASH_H */ diff --git a/wolfHAL/crypto/stm32wba_aes.h b/wolfHAL/crypto/stm32wba_aes.h index 080bb0d..d5f1cfe 100644 --- a/wolfHAL/crypto/stm32wba_aes.h +++ b/wolfHAL/crypto/stm32wba_aes.h @@ -55,5 +55,14 @@ typedef whal_Stm32wb_AesCcm_State whal_Stm32wba_AesCcm_State; #define whal_Stm32wba_Aes_GmacDriver whal_Stm32wb_Aes_GmacDriver #define whal_Stm32wba_Aes_CcmDriver whal_Stm32wb_Aes_CcmDriver +/* Config initializer macro aliases. The WBA board.h supplies the bodies + * under WBA-prefixed names; the WB driver source consumes the WB names. */ +#define WHAL_CFG_STM32WB_AES_DEV WHAL_CFG_STM32WBA_AES_DEV +#define WHAL_CFG_STM32WB_AES_ECB_DEV WHAL_CFG_STM32WBA_AES_ECB_DEV +#define WHAL_CFG_STM32WB_AES_CBC_DEV WHAL_CFG_STM32WBA_AES_CBC_DEV +#define WHAL_CFG_STM32WB_AES_CTR_DEV WHAL_CFG_STM32WBA_AES_CTR_DEV +#define WHAL_CFG_STM32WB_AES_GCM_DEV WHAL_CFG_STM32WBA_AES_GCM_DEV +#define WHAL_CFG_STM32WB_AES_GMAC_DEV WHAL_CFG_STM32WBA_AES_GMAC_DEV +#define WHAL_CFG_STM32WB_AES_CCM_DEV WHAL_CFG_STM32WBA_AES_CCM_DEV #endif /* WHAL_STM32WBA_AES_H */ diff --git a/wolfHAL/dma/stm32u5_gpdma.h b/wolfHAL/dma/stm32u5_gpdma.h new file mode 100644 index 0000000..cba1783 --- /dev/null +++ b/wolfHAL/dma/stm32u5_gpdma.h @@ -0,0 +1,70 @@ +/* stm32u5_gpdma.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_GPDMA_H +#define WHAL_STM32U5_GPDMA_H + +/** + * @file stm32u5_gpdma.h + * @brief STM32U5 GPDMA driver (alias for STM32WBA GPDMA). + * + * The STM32U5 GPDMA controller is register-compatible with the STM32WBA + * GPDMA. This header re-exports the STM32WBA GPDMA driver types and symbols + * under STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wba_Gpdma_Dir whal_Stm32u5_Gpdma_Dir; +typedef whal_Stm32wba_Gpdma_Width whal_Stm32u5_Gpdma_Width; +typedef whal_Stm32wba_Gpdma_Inc whal_Stm32u5_Gpdma_Inc; +typedef whal_Stm32wba_Gpdma_ChCfg whal_Stm32u5_Gpdma_ChCfg; +typedef whal_Stm32wba_Gpdma_Cfg whal_Stm32u5_Gpdma_Cfg; +typedef whal_Stm32wba_Gpdma_Callback whal_Stm32u5_Gpdma_Callback; + +#define whal_Stm32u5_Gpdma_Dev whal_Stm32wba_Gpdma_Dev + +#ifndef WHAL_CFG_STM32U5_GPDMA_DIRECT_API_MAPPING +#define whal_Stm32u5_Gpdma_Driver whal_Stm32wba_Gpdma_Driver +#define whal_Stm32u5_Gpdma_IRQHandler whal_Stm32wba_Gpdma_IRQHandler +#endif /* !WHAL_CFG_STM32U5_GPDMA_DIRECT_API_MAPPING */ + +/** + * @brief Transfer direction (re-exported from STM32WBA). + */ +#define WHAL_STM32U5_GPDMA_DIR_PERIPH_TO_MEM WHAL_STM32WBA_GPDMA_DIR_PERIPH_TO_MEM +#define WHAL_STM32U5_GPDMA_DIR_MEM_TO_PERIPH WHAL_STM32WBA_GPDMA_DIR_MEM_TO_PERIPH +#define WHAL_STM32U5_GPDMA_DIR_MEM_TO_MEM WHAL_STM32WBA_GPDMA_DIR_MEM_TO_MEM + +/** + * @brief Data width (re-exported from STM32WBA). + */ +#define WHAL_STM32U5_GPDMA_WIDTH_8BIT WHAL_STM32WBA_GPDMA_WIDTH_8BIT +#define WHAL_STM32U5_GPDMA_WIDTH_16BIT WHAL_STM32WBA_GPDMA_WIDTH_16BIT +#define WHAL_STM32U5_GPDMA_WIDTH_32BIT WHAL_STM32WBA_GPDMA_WIDTH_32BIT + +/** + * @brief Address increment (re-exported from STM32WBA). + */ +#define WHAL_STM32U5_GPDMA_INC_DISABLE WHAL_STM32WBA_GPDMA_INC_DISABLE +#define WHAL_STM32U5_GPDMA_INC_ENABLE WHAL_STM32WBA_GPDMA_INC_ENABLE + +#endif /* WHAL_STM32U5_GPDMA_H */ diff --git a/wolfHAL/flash/stm32f3_flash.h b/wolfHAL/flash/stm32f3_flash.h index 4898b6f..0146975 100644 --- a/wolfHAL/flash/stm32f3_flash.h +++ b/wolfHAL/flash/stm32f3_flash.h @@ -54,4 +54,8 @@ typedef whal_Stm32f0_Flash_Cfg whal_Stm32f3_Flash_Cfg; #define whal_Stm32f3_Flash_Ext_SetLatency whal_Stm32f0_Flash_Ext_SetLatency +/* Config initializer macro alias. The F3 board.h supplies the body under + * the F3-prefixed name; the F0 driver source consumes the F0 name. */ +#define WHAL_CFG_STM32F0_FLASH_DEV WHAL_CFG_STM32F3_FLASH_DEV + #endif /* WHAL_STM32F3_FLASH_H */ diff --git a/wolfHAL/flash/stm32u5_flash.h b/wolfHAL/flash/stm32u5_flash.h new file mode 100644 index 0000000..f64237e --- /dev/null +++ b/wolfHAL/flash/stm32u5_flash.h @@ -0,0 +1,123 @@ +/* stm32u5_flash.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_FLASH_H +#define WHAL_STM32U5_FLASH_H + +#include +#include + +/** + * @file stm32u5_flash.h + * @brief STM32U5 flash driver configuration. + * + * The STM32U5 embedded flash provides: + * - Up to 4 MB organized in 8 KB pages, always dual-bank on production parts + * - 128-bit (flash-word) programming, 16-byte aligned + * - Non-secure register variants (NSCR, NSSR, NSKEYR) + * - TrustZone support (this driver uses non-secure registers) + * + * Key register differences from STM32WBA: + * - NSCR PNB field is 8 bits (PNB[7:0]) at bits 10:3 (vs 7 bits at 9:3 on WBA) + * - NSCR adds BKER (bit 11) for dual-bank page selection + * - NSCR adds MER1 (bit 2) and MER2 (bit 15) for per-bank mass erase + * + * Bank layout is part-dependent: + * - 1 MB U575/U585 variants: 512 KB per bank, 64 pages per bank. + * - 2 MB U575/U585 variants: 1 MB per bank, 128 pages per bank. + * - 4 MB U59x/U5Ax/U5Fx/U5Gx variants: 2 MB per bank, 256 pages per bank. + * Bank 2 lives immediately after bank 1 in the address space and is selected + * with BKER=1. The board.h flash config provides the actual bank size for + * the chip in use; the constants below are defaults used when bankSize is 0. + */ + +#define WHAL_STM32U5_FLASH_BANK_SIZE 0x00200000 /* 2 MB per bank on U5Ax */ +#define WHAL_STM32U5_FLASH_PAGE_SIZE 0x2000 /* 8 KB */ + +/** + * @brief STM32U5 flash driver configuration. + */ +typedef struct whal_Stm32u5_Flash_Cfg { + size_t startAddr; /**< Flash region start address (typ 0x08000000) */ + size_t size; /**< Flash region size in bytes */ + size_t bankSize; /**< Size of one bank (typ 512 KB on 1 MB part) */ + whal_Timeout *timeout; /**< Timeout for poll loops */ +} whal_Stm32u5_Flash_Cfg; + +/** + * @brief Driver instance for the STM32U5 embedded flash controller. + */ +extern const whal_FlashDriver whal_Stm32u5_Flash_Driver; + +/** + * @brief Platform-owned device singleton. Defined in the driver TU + * from the WHAL_CFG_STM32U5_FLASH_DEV initializer in board.h. + */ +extern const whal_Flash whal_Stm32u5_Flash_Dev; + +/** + * @brief Initialize the STM32U5 flash driver. + */ +whal_Error whal_Stm32u5_Flash_Init(whal_Flash *flashDev); + +/** + * @brief Deinitialize the STM32U5 flash driver. + */ +whal_Error whal_Stm32u5_Flash_Deinit(whal_Flash *flashDev); + +/** + * @brief Re-lock the STM32U5 flash for writes (sets NSCR.LOCK). + */ +whal_Error whal_Stm32u5_Flash_Lock(whal_Flash *flashDev, size_t addr, size_t len); + +/** + * @brief Unlock the STM32U5 flash for writes via the NSKEYR sequence. + * Checks LOCK first to avoid double-unlock hard-fault. + */ +whal_Error whal_Stm32u5_Flash_Unlock(whal_Flash *flashDev, size_t addr, size_t len); + +/** + * @brief Read `dataSz` bytes from flash at `addr` into `data`. + */ +whal_Error whal_Stm32u5_Flash_Read(whal_Flash *flashDev, size_t addr, + void *data, size_t dataSz); + +/** + * @brief Program `dataSz` bytes from `data` to flash at `addr`. Address and + * size must be 128-bit (flash-word) aligned. + */ +whal_Error whal_Stm32u5_Flash_Write(whal_Flash *flashDev, size_t addr, + const void *data, size_t dataSz); + +/** + * @brief Erase one or more 8 KB pages covering [addr, addr+dataSz). + * Handles dual-bank page numbering (BKER + PNB[7:0]). + */ +whal_Error whal_Stm32u5_Flash_Erase(whal_Flash *flashDev, size_t addr, size_t dataSz); + +/** + * @brief Set the flash wait-state latency in FLASH_ACR.LATENCY. + * Must be programmed before raising HCLK above the previous latency's + * maximum supported frequency. + */ +whal_Error whal_Stm32u5_Flash_Ext_SetLatency(whal_Flash *flashDev, uint8_t latency); + +#endif /* WHAL_STM32U5_FLASH_H */ diff --git a/wolfHAL/gpio/stm32c0_gpio.h b/wolfHAL/gpio/stm32c0_gpio.h index 33d2f24..ff20ee4 100644 --- a/wolfHAL/gpio/stm32c0_gpio.h +++ b/wolfHAL/gpio/stm32c0_gpio.h @@ -90,4 +90,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32c0_Gpio_PinCfg; */ #define WHAL_STM32C0_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The C0 board.h supplies the body under + * the C0-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32C0_GPIO_DEV + #endif /* WHAL_STM32C0_GPIO_H */ diff --git a/wolfHAL/gpio/stm32f0_gpio.h b/wolfHAL/gpio/stm32f0_gpio.h index 87433f9..a4a134f 100644 --- a/wolfHAL/gpio/stm32f0_gpio.h +++ b/wolfHAL/gpio/stm32f0_gpio.h @@ -72,4 +72,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f0_Gpio_PinCfg; #define WHAL_STM32F0_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The F0 board.h supplies the body under + * the F0-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32F0_GPIO_DEV + #endif /* WHAL_STM32F0_GPIO_H */ diff --git a/wolfHAL/gpio/stm32f3_gpio.h b/wolfHAL/gpio/stm32f3_gpio.h index ed2eb6c..d95cc4d 100644 --- a/wolfHAL/gpio/stm32f3_gpio.h +++ b/wolfHAL/gpio/stm32f3_gpio.h @@ -72,4 +72,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f3_Gpio_PinCfg; #define WHAL_STM32F3_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The F3 board.h supplies the body under + * the F3-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32F3_GPIO_DEV + #endif /* WHAL_STM32F3_GPIO_H */ diff --git a/wolfHAL/gpio/stm32f4_gpio.h b/wolfHAL/gpio/stm32f4_gpio.h index f874fde..4a86088 100644 --- a/wolfHAL/gpio/stm32f4_gpio.h +++ b/wolfHAL/gpio/stm32f4_gpio.h @@ -93,4 +93,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32f4_Gpio_PinCfg; */ #define WHAL_STM32F4_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The F4 board.h supplies the body under + * the F4-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32F4_GPIO_DEV + #endif /* WHAL_STM32F4_GPIO_H */ diff --git a/wolfHAL/gpio/stm32h5_gpio.h b/wolfHAL/gpio/stm32h5_gpio.h index 3a26a32..a81fc5c 100644 --- a/wolfHAL/gpio/stm32h5_gpio.h +++ b/wolfHAL/gpio/stm32h5_gpio.h @@ -94,4 +94,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32h5_Gpio_PinCfg; */ #define WHAL_STM32H5_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The H5 board.h supplies the body under + * the H5-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32H5_GPIO_DEV + #endif /* WHAL_STM32H5_GPIO_H */ diff --git a/wolfHAL/gpio/stm32l1_gpio.h b/wolfHAL/gpio/stm32l1_gpio.h index cda71e6..0d9b0fe 100644 --- a/wolfHAL/gpio/stm32l1_gpio.h +++ b/wolfHAL/gpio/stm32l1_gpio.h @@ -74,4 +74,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32l1_Gpio_PinCfg; #define WHAL_STM32L1_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The L1 board.h supplies the body under + * the L1-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32L1_GPIO_DEV + #endif /* WHAL_STM32L1_GPIO_H */ diff --git a/wolfHAL/gpio/stm32n6_gpio.h b/wolfHAL/gpio/stm32n6_gpio.h index 549c66e..c653bc5 100644 --- a/wolfHAL/gpio/stm32n6_gpio.h +++ b/wolfHAL/gpio/stm32n6_gpio.h @@ -74,4 +74,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32n6_Gpio_PinCfg; #define WHAL_STM32N6_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The N6 board.h supplies the body under + * the N6-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32N6_GPIO_DEV + #endif /* WHAL_STM32N6_GPIO_H */ diff --git a/wolfHAL/gpio/stm32u5_gpio.h b/wolfHAL/gpio/stm32u5_gpio.h new file mode 100644 index 0000000..09e457c --- /dev/null +++ b/wolfHAL/gpio/stm32u5_gpio.h @@ -0,0 +1,100 @@ +/* stm32u5_gpio.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_GPIO_H +#define WHAL_STM32U5_GPIO_H + +/** + * @file stm32u5_gpio.h + * @brief STM32U5 GPIO driver (alias for STM32WB GPIO). + * + * The STM32U5 GPIO peripheral is register-compatible with the STM32WB GPIO. + * This header re-exports the STM32WB GPIO driver types and symbols under + * STM32U5-specific names. The underlying implementation is shared. + */ + +#include + +typedef whal_Stm32wb_Gpio_Cfg whal_Stm32u5_Gpio_Cfg; +typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32u5_Gpio_PinCfg; + +#define whal_Stm32u5_Gpio_Dev whal_Stm32wb_Gpio_Dev + +#ifndef WHAL_CFG_STM32U5_GPIO_DIRECT_API_MAPPING +#define whal_Stm32u5_Gpio_Driver whal_Stm32wb_Gpio_Driver +#define whal_Stm32u5_Gpio_Init whal_Stm32wb_Gpio_Init +#define whal_Stm32u5_Gpio_Deinit whal_Stm32wb_Gpio_Deinit +#define whal_Stm32u5_Gpio_Get whal_Stm32wb_Gpio_Get +#define whal_Stm32u5_Gpio_Set whal_Stm32wb_Gpio_Set +#endif /* !WHAL_CFG_STM32U5_GPIO_DIRECT_API_MAPPING */ + +/** + * @brief GPIO mode selection (re-exported from STM32WB). + */ +#define WHAL_STM32U5_GPIO_MODE_IN WHAL_STM32WB_GPIO_MODE_IN +#define WHAL_STM32U5_GPIO_MODE_OUT WHAL_STM32WB_GPIO_MODE_OUT +#define WHAL_STM32U5_GPIO_MODE_ALTFN WHAL_STM32WB_GPIO_MODE_ALTFN +#define WHAL_STM32U5_GPIO_MODE_ANALOG WHAL_STM32WB_GPIO_MODE_ANALOG + +/** + * @brief GPIO output type (re-exported from STM32WB). + */ +#define WHAL_STM32U5_GPIO_OUTTYPE_PUSHPULL WHAL_STM32WB_GPIO_OUTTYPE_PUSHPULL +#define WHAL_STM32U5_GPIO_OUTTYPE_OPENDRAIN WHAL_STM32WB_GPIO_OUTTYPE_OPENDRAIN + +/** + * @brief GPIO speed selection (re-exported from STM32WB). + */ +#define WHAL_STM32U5_GPIO_SPEED_LOW WHAL_STM32WB_GPIO_SPEED_LOW +#define WHAL_STM32U5_GPIO_SPEED_MEDIUM WHAL_STM32WB_GPIO_SPEED_MEDIUM +#define WHAL_STM32U5_GPIO_SPEED_FAST WHAL_STM32WB_GPIO_SPEED_FAST +#define WHAL_STM32U5_GPIO_SPEED_HIGH WHAL_STM32WB_GPIO_SPEED_HIGH + +/** + * @brief GPIO pull-up/pull-down selection (re-exported from STM32WB). + */ +#define WHAL_STM32U5_GPIO_PULL_NONE WHAL_STM32WB_GPIO_PULL_NONE +#define WHAL_STM32U5_GPIO_PULL_UP WHAL_STM32WB_GPIO_PULL_UP +#define WHAL_STM32U5_GPIO_PULL_DOWN WHAL_STM32WB_GPIO_PULL_DOWN + +/** + * @brief GPIO port selection (re-exported from STM32WB). + */ +#define WHAL_STM32U5_GPIO_PORT_A WHAL_STM32WB_GPIO_PORT_A +#define WHAL_STM32U5_GPIO_PORT_B WHAL_STM32WB_GPIO_PORT_B +#define WHAL_STM32U5_GPIO_PORT_C WHAL_STM32WB_GPIO_PORT_C +#define WHAL_STM32U5_GPIO_PORT_D WHAL_STM32WB_GPIO_PORT_D +#define WHAL_STM32U5_GPIO_PORT_E WHAL_STM32WB_GPIO_PORT_E +#define WHAL_STM32U5_GPIO_PORT_F WHAL_STM32WB_GPIO_PORT_F +#define WHAL_STM32U5_GPIO_PORT_G WHAL_STM32WB_GPIO_PORT_G +#define WHAL_STM32U5_GPIO_PORT_H WHAL_STM32WB_GPIO_PORT_H + +/** + * @brief Pack a GPIO pin configuration into a single word (re-exported from + * STM32WB). + */ +#define WHAL_STM32U5_GPIO_PIN WHAL_STM32WB_GPIO_PIN + +/* Config initializer macro alias. The U5 board.h supplies the body under + * the U5-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32U5_GPIO_DEV + +#endif /* WHAL_STM32U5_GPIO_H */ diff --git a/wolfHAL/gpio/stm32wba_gpio.h b/wolfHAL/gpio/stm32wba_gpio.h index a2020b6..b255d07 100644 --- a/wolfHAL/gpio/stm32wba_gpio.h +++ b/wolfHAL/gpio/stm32wba_gpio.h @@ -89,4 +89,8 @@ typedef whal_Stm32wb_Gpio_PinCfg whal_Stm32wba_Gpio_PinCfg; */ #define WHAL_STM32WBA_GPIO_PIN WHAL_STM32WB_GPIO_PIN +/* Config initializer macro alias. The WBA board.h supplies the body under + * the WBA-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_GPIO_DEV WHAL_CFG_STM32WBA_GPIO_DEV + #endif /* WHAL_STM32WBA_GPIO_H */ diff --git a/wolfHAL/i2c/stm32u5_i2c.h b/wolfHAL/i2c/stm32u5_i2c.h new file mode 100644 index 0000000..e30f152 --- /dev/null +++ b/wolfHAL/i2c/stm32u5_i2c.h @@ -0,0 +1,49 @@ +/* stm32u5_i2c.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_I2C_H +#define WHAL_STM32U5_I2C_H + +/** + * @file stm32u5_i2c.h + * @brief STM32U5 I2C driver (alias for STM32WB I2C). + * + * The STM32U5 I2C peripheral is register-compatible with the STM32WB I2C. + * This header re-exports the STM32WB I2C driver types and symbols under + * STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wb_I2c_Cfg whal_Stm32u5_I2c_Cfg; + +#define whal_Stm32u5_I2c_Dev whal_Stm32wb_I2c_Dev + +#ifndef WHAL_CFG_STM32U5_I2C_DIRECT_API_MAPPING +#define whal_Stm32u5_I2c_Driver whal_Stm32wb_I2c_Driver +#define whal_Stm32u5_I2c_Init whal_Stm32wb_I2c_Init +#define whal_Stm32u5_I2c_Deinit whal_Stm32wb_I2c_Deinit +#define whal_Stm32u5_I2c_StartCom whal_Stm32wb_I2c_StartCom +#define whal_Stm32u5_I2c_EndCom whal_Stm32wb_I2c_EndCom +#define whal_Stm32u5_I2c_Transfer whal_Stm32wb_I2c_Transfer +#endif /* !WHAL_CFG_STM32U5_I2C_DIRECT_API_MAPPING */ + +#endif /* WHAL_STM32U5_I2C_H */ diff --git a/wolfHAL/platform/st/stm32u5a5zj.h b/wolfHAL/platform/st/stm32u5a5zj.h new file mode 100644 index 0000000..79795e4 --- /dev/null +++ b/wolfHAL/platform/st/stm32u5a5zj.h @@ -0,0 +1,322 @@ +/* stm32u5a5zj.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5A5ZJ_H +#define WHAL_STM32U5A5ZJ_H + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * @file stm32u5a5zj.h + * @brief Convenience initializers for STM32U5A5ZJ device instances. + * + * Base addresses from RM0456 Table 6 (memory map and peripheral register + * boundary addresses). + * + * GPIO: 0x42020000 (port A), 0x400 spacing per port (A..H) + * RCC: 0x46020C00 + * PWR: 0x46020800 + * USART1: 0x40013800 + * SPI1: 0x40013000 + * I2C1: 0x40005400 + * Flash interface: 0x40022000 + * RNG: 0x420C0800 + * AES: 0x420C0000 + * HASH: 0x420C0400 + * GPDMA1: 0x40020000 + */ + +/* --- Regmap and driver macros --- */ + +#define WHAL_STM32U5A5_GPIO_BASE 0x42020000 +#define WHAL_STM32U5A5_GPIO_DRIVER &whal_Stm32u5_Gpio_Driver + +#define WHAL_STM32U5A5_USART1_BASE 0x40013800 +#define WHAL_STM32U5A5_USART1_DRIVER &whal_Stm32u5_Uart_Driver + +#define WHAL_STM32U5A5_USART2_BASE 0x40004400 +#define WHAL_STM32U5A5_USART2_DRIVER &whal_Stm32u5_Uart_Driver + +#define WHAL_STM32U5A5_USART3_BASE 0x40004800 +#define WHAL_STM32U5A5_USART3_DRIVER &whal_Stm32u5_Uart_Driver + +#define WHAL_STM32U5A5_LPUART1_BASE 0x46002400 +#define WHAL_STM32U5A5_LPUART1_DRIVER &whal_Stm32u5_Uart_Driver + +#define WHAL_STM32U5A5_SPI1_BASE 0x40013000 +#define WHAL_STM32U5A5_SPI1_DRIVER &whal_Stm32u5_Spi_Driver + +#define WHAL_STM32U5A5_SPI2_BASE 0x40003800 +#define WHAL_STM32U5A5_SPI2_DRIVER &whal_Stm32u5_Spi_Driver + +#define WHAL_STM32U5A5_SPI3_BASE 0x46002000 +#define WHAL_STM32U5A5_SPI3_DRIVER &whal_Stm32u5_Spi_Driver + +#define WHAL_STM32U5A5_I2C1_BASE 0x40005400 +#define WHAL_STM32U5A5_I2C1_DRIVER &whal_Stm32u5_I2c_Driver + +#define WHAL_STM32U5A5_I2C2_BASE 0x40005800 +#define WHAL_STM32U5A5_I2C2_DRIVER &whal_Stm32u5_I2c_Driver + +#define WHAL_STM32U5A5_I2C3_BASE 0x46002800 +#define WHAL_STM32U5A5_I2C3_DRIVER &whal_Stm32u5_I2c_Driver + +#define WHAL_STM32U5A5_I2C4_BASE 0x40008400 +#define WHAL_STM32U5A5_I2C4_DRIVER &whal_Stm32u5_I2c_Driver + +#define WHAL_STM32U5A5_FLASH_BASE 0x40022000 +#define WHAL_STM32U5A5_FLASH_DRIVER &whal_Stm32u5_Flash_Driver + +#define WHAL_STM32U5A5_RNG_BASE 0x420C0800 +#define WHAL_STM32U5A5_RNG_DRIVER &whal_Stm32u5_Rng_Driver + +#define WHAL_STM32U5A5_GPDMA1_BASE 0x40020000 +#define WHAL_STM32U5A5_GPDMA1_DRIVER &whal_Stm32u5_Gpdma_Driver + +#define WHAL_STM32U5A5_AES_BASE 0x420C0000 +#define WHAL_STM32U5A5_AES_DRIVER &whal_Stm32u5_Aes_CryptoDriver + +#define WHAL_STM32U5A5_HASH_BASE 0x420C0400 +#define WHAL_STM32U5A5_HASH_DRIVER &whal_Stm32u5_Hash_CryptoDriver + +#define WHAL_STM32U5A5_IWDG_BASE 0x40003000 +#define WHAL_STM32U5A5_IWDG_DRIVER &whal_Stm32u5_Iwdg_Driver + +#define WHAL_STM32U5A5_WWDG_BASE 0x40002C00 +#define WHAL_STM32U5A5_WWDG_DRIVER &whal_Stm32u5_Wwdg_Driver + +/* --- Clock gate macros --- */ +/* RCC base: 0x46020C00, offsets from base */ + +/* RCC_AHB1ENR (offset 0x088) */ +#define WHAL_STM32U5A5_GPDMA1_CLOCK \ + .regOffset = 0x088, \ + .enableMask = (1UL << 0), \ + .enablePos = 0 + +#define WHAL_STM32U5A5_FLASH_CLOCK \ + .regOffset = 0x088, \ + .enableMask = (1UL << 8), \ + .enablePos = 8 + +/* USART1 TX DMA configuration: memory-to-peripheral, 8-bit, REQSEL=USART1_TX */ +#define WHAL_STM32U5A5_USART1_TX_DMA_CFG \ + .dir = WHAL_STM32U5_GPDMA_DIR_MEM_TO_PERIPH, \ + .srcWidth = WHAL_STM32U5_GPDMA_WIDTH_8BIT, \ + .dstWidth = WHAL_STM32U5_GPDMA_WIDTH_8BIT, \ + .srcInc = WHAL_STM32U5_GPDMA_INC_ENABLE, \ + .dstInc = WHAL_STM32U5_GPDMA_INC_DISABLE, \ + .reqSel = 27 + +/* USART1 RX DMA configuration: peripheral-to-memory, 8-bit, REQSEL=USART1_RX */ +#define WHAL_STM32U5A5_USART1_RX_DMA_CFG \ + .dir = WHAL_STM32U5_GPDMA_DIR_PERIPH_TO_MEM, \ + .srcWidth = WHAL_STM32U5_GPDMA_WIDTH_8BIT, \ + .dstWidth = WHAL_STM32U5_GPDMA_WIDTH_8BIT, \ + .srcInc = WHAL_STM32U5_GPDMA_INC_DISABLE, \ + .dstInc = WHAL_STM32U5_GPDMA_INC_ENABLE, \ + .reqSel = 26 + +/* RCC_AHB2ENR1 (offset 0x08C) */ +#define WHAL_STM32U5A5_GPIOA_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 0), \ + .enablePos = 0 + +#define WHAL_STM32U5A5_GPIOB_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 1), \ + .enablePos = 1 + +#define WHAL_STM32U5A5_GPIOC_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 2), \ + .enablePos = 2 + +#define WHAL_STM32U5A5_GPIOD_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 3), \ + .enablePos = 3 + +#define WHAL_STM32U5A5_GPIOE_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 4), \ + .enablePos = 4 + +#define WHAL_STM32U5A5_GPIOF_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 5), \ + .enablePos = 5 + +#define WHAL_STM32U5A5_GPIOG_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 6), \ + .enablePos = 6 + +#define WHAL_STM32U5A5_GPIOH_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 7), \ + .enablePos = 7 + +#define WHAL_STM32U5A5_AES_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 16), \ + .enablePos = 16 + +#define WHAL_STM32U5A5_HASH_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 17), \ + .enablePos = 17 + +#define WHAL_STM32U5A5_RNG_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 18), \ + .enablePos = 18 + +#define WHAL_STM32U5A5_SAES_CLOCK \ + .regOffset = 0x08C, \ + .enableMask = (1UL << 20), \ + .enablePos = 20 + +/* RCC_AHB3ENR (offset 0x094) — PWR, ADC4, LPGPIO1, LPDMA1 live here on U5. */ +#define WHAL_STM32U5A5_PWR_CLOCK \ + .regOffset = 0x094, \ + .enableMask = (1UL << 2), \ + .enablePos = 2 + +#define WHAL_STM32U5A5_ADC4_CLOCK \ + .regOffset = 0x094, \ + .enableMask = (1UL << 5), \ + .enablePos = 5 + +/* RCC_APB1ENR1 (offset 0x09C) */ +#define WHAL_STM32U5A5_TIM2_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 0), \ + .enablePos = 0 + +#define WHAL_STM32U5A5_TIM3_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 1), \ + .enablePos = 1 + +#define WHAL_STM32U5A5_WWDG_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 11), \ + .enablePos = 11 + +#define WHAL_STM32U5A5_SPI2_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 14), \ + .enablePos = 14 + +#define WHAL_STM32U5A5_USART2_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 17), \ + .enablePos = 17 + +#define WHAL_STM32U5A5_USART3_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 18), \ + .enablePos = 18 + +#define WHAL_STM32U5A5_I2C1_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 21), \ + .enablePos = 21 + +#define WHAL_STM32U5A5_I2C2_CLOCK \ + .regOffset = 0x09C, \ + .enableMask = (1UL << 22), \ + .enablePos = 22 + +/* RCC_APB1ENR2 (offset 0x0A0) */ +#define WHAL_STM32U5A5_I2C4_CLOCK \ + .regOffset = 0x0A0, \ + .enableMask = (1UL << 1), \ + .enablePos = 1 + +/* RCC_APB2ENR (offset 0x0A4) */ +#define WHAL_STM32U5A5_TIM1_CLOCK \ + .regOffset = 0x0A4, \ + .enableMask = (1UL << 11), \ + .enablePos = 11 + +#define WHAL_STM32U5A5_SPI1_CLOCK \ + .regOffset = 0x0A4, \ + .enableMask = (1UL << 12), \ + .enablePos = 12 + +#define WHAL_STM32U5A5_USART1_CLOCK \ + .regOffset = 0x0A4, \ + .enableMask = (1UL << 14), \ + .enablePos = 14 + +#define WHAL_STM32U5A5_TIM16_CLOCK \ + .regOffset = 0x0A4, \ + .enableMask = (1UL << 17), \ + .enablePos = 17 + +#define WHAL_STM32U5A5_TIM17_CLOCK \ + .regOffset = 0x0A4, \ + .enableMask = (1UL << 18), \ + .enablePos = 18 + +/* RCC_APB3ENR (offset 0x0A8) */ +#define WHAL_STM32U5A5_SYSCFG_CLOCK \ + .regOffset = 0x0A8, \ + .enableMask = (1UL << 1), \ + .enablePos = 1 + +#define WHAL_STM32U5A5_SPI3_CLOCK \ + .regOffset = 0x0A8, \ + .enableMask = (1UL << 5), \ + .enablePos = 5 + +#define WHAL_STM32U5A5_LPUART1_CLOCK \ + .regOffset = 0x0A8, \ + .enableMask = (1UL << 6), \ + .enablePos = 6 + +#define WHAL_STM32U5A5_I2C3_CLOCK \ + .regOffset = 0x0A8, \ + .enableMask = (1UL << 7), \ + .enablePos = 7 + +#define WHAL_STM32U5A5_LPTIM1_CLOCK \ + .regOffset = 0x0A8, \ + .enableMask = (1UL << 11), \ + .enablePos = 11 + +#endif /* WHAL_STM32U5A5ZJ_H */ diff --git a/wolfHAL/rng/stm32n6_rng.h b/wolfHAL/rng/stm32n6_rng.h index b10cb0d..e42503c 100644 --- a/wolfHAL/rng/stm32n6_rng.h +++ b/wolfHAL/rng/stm32n6_rng.h @@ -44,4 +44,8 @@ typedef whal_Stm32wba_Rng_Cfg whal_Stm32n6_Rng_Cfg; #define whal_Stm32n6_Rng_Generate whal_Stm32wba_Rng_Generate #endif /* !WHAL_CFG_STM32N6_RNG_DIRECT_API_MAPPING */ +/* Config initializer macro alias. The N6 board.h supplies the body under + * the N6-prefixed name; the WBA driver source consumes the WBA name. */ +#define WHAL_CFG_STM32WBA_RNG_DEV WHAL_CFG_STM32N6_RNG_DEV + #endif /* WHAL_STM32N6_RNG_H */ diff --git a/wolfHAL/rng/stm32u5_rng.h b/wolfHAL/rng/stm32u5_rng.h new file mode 100644 index 0000000..95e432b --- /dev/null +++ b/wolfHAL/rng/stm32u5_rng.h @@ -0,0 +1,52 @@ +/* stm32u5_rng.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_RNG_H +#define WHAL_STM32U5_RNG_H + +/** + * @file stm32u5_rng.h + * @brief STM32U5 RNG driver (alias for STM32WBA RNG). + * + * The STM32U5 RNG peripheral is register-compatible with the STM32WBA RNG + * (CONDRST/CONFIGLOCK + NIST SP800-90B health check sequence). This header + * re-exports the STM32WBA RNG driver types and symbols under STM32U5-specific + * names. + */ + +#include + +typedef whal_Stm32wba_Rng_Cfg whal_Stm32u5_Rng_Cfg; + +#define whal_Stm32u5_Rng_Dev whal_Stm32wba_Rng_Dev + +#ifndef WHAL_CFG_STM32U5_RNG_DIRECT_API_MAPPING +#define whal_Stm32u5_Rng_Driver whal_Stm32wba_Rng_Driver +#define whal_Stm32u5_Rng_Init whal_Stm32wba_Rng_Init +#define whal_Stm32u5_Rng_Deinit whal_Stm32wba_Rng_Deinit +#define whal_Stm32u5_Rng_Generate whal_Stm32wba_Rng_Generate +#endif /* !WHAL_CFG_STM32U5_RNG_DIRECT_API_MAPPING */ + +/* Config initializer macro alias. The U5 board.h supplies the body under + * the U5-prefixed name; the WBA driver source consumes the WBA name. */ +#define WHAL_CFG_STM32WBA_RNG_DEV WHAL_CFG_STM32U5_RNG_DEV + +#endif /* WHAL_STM32U5_RNG_H */ diff --git a/wolfHAL/spi/stm32u5_spi.h b/wolfHAL/spi/stm32u5_spi.h new file mode 100644 index 0000000..f390cf7 --- /dev/null +++ b/wolfHAL/spi/stm32u5_spi.h @@ -0,0 +1,47 @@ +/* stm32u5_spi.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_SPI_H +#define WHAL_STM32U5_SPI_H + +/** + * @file stm32u5_spi.h + * @brief STM32U5 SPI driver (alias for STM32H5 SPI). + * + * The STM32U5 SPI peripheral is register-compatible with the STM32H5 SPI + * (V2 SPI). This header re-exports the STM32H5 SPI driver types and symbols + * under STM32U5-specific names. + */ + +#include + +typedef whal_Stm32h5_Spi_Cfg whal_Stm32u5_Spi_Cfg; + +#ifndef WHAL_CFG_STM32U5_SPI_DIRECT_API_MAPPING +#define whal_Stm32u5_Spi_Driver whal_Stm32h5_Spi_Driver +#define whal_Stm32u5_Spi_Init whal_Stm32h5_Spi_Init +#define whal_Stm32u5_Spi_Deinit whal_Stm32h5_Spi_Deinit +#define whal_Stm32u5_Spi_StartCom whal_Stm32h5_Spi_StartCom +#define whal_Stm32u5_Spi_EndCom whal_Stm32h5_Spi_EndCom +#define whal_Stm32u5_Spi_SendRecv whal_Stm32h5_Spi_SendRecv +#endif /* !WHAL_CFG_STM32U5_SPI_DIRECT_API_MAPPING */ + +#endif /* WHAL_STM32U5_SPI_H */ diff --git a/wolfHAL/uart/stm32u5_uart.h b/wolfHAL/uart/stm32u5_uart.h new file mode 100644 index 0000000..5187cbb --- /dev/null +++ b/wolfHAL/uart/stm32u5_uart.h @@ -0,0 +1,54 @@ +/* stm32u5_uart.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_UART_H +#define WHAL_STM32U5_UART_H + +/** + * @file stm32u5_uart.h + * @brief STM32U5 UART driver (alias for STM32WB UART). + * + * The STM32U5 USART peripheral is register-compatible with the STM32WB USART + * (FIFO USART variant). This header re-exports the STM32WB UART driver types + * and symbols under STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wb_Uart_Cfg whal_Stm32u5_Uart_Cfg; + +#define whal_Stm32u5_Uart_Dev whal_Stm32wb_Uart_Dev + +#ifndef WHAL_CFG_STM32U5_UART_DIRECT_API_MAPPING +#define whal_Stm32u5_Uart_Driver whal_Stm32wb_Uart_Driver +#define whal_Stm32u5_Uart_Init whal_Stm32wb_Uart_Init +#define whal_Stm32u5_Uart_Deinit whal_Stm32wb_Uart_Deinit +#define whal_Stm32u5_Uart_Send whal_Stm32wb_Uart_Send +#define whal_Stm32u5_Uart_Recv whal_Stm32wb_Uart_Recv +#endif /* !WHAL_CFG_STM32U5_UART_DIRECT_API_MAPPING */ + +/** + * @brief Baud rate register helpers (re-exported from STM32WB). + */ +#define WHAL_STM32U5_UART_BRR WHAL_STM32WB_UART_BRR +#define WHAL_STM32U5_LPUART_BRR WHAL_STM32WB_LPUART_BRR + +#endif /* WHAL_STM32U5_UART_H */ diff --git a/wolfHAL/watchdog/stm32f0_iwdg.h b/wolfHAL/watchdog/stm32f0_iwdg.h index f609b3b..287ae7a 100644 --- a/wolfHAL/watchdog/stm32f0_iwdg.h +++ b/wolfHAL/watchdog/stm32f0_iwdg.h @@ -52,4 +52,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32f0_Iwdg_Cfg; #define WHAL_STM32F0_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 #define WHAL_STM32F0_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 +/* Config initializer macro alias. The F0 board.h supplies the body under + * the F0-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32F0_IWDG_DEV + #endif /* WHAL_STM32F0_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32f3_iwdg.h b/wolfHAL/watchdog/stm32f3_iwdg.h index 1df2688..52e919a 100644 --- a/wolfHAL/watchdog/stm32f3_iwdg.h +++ b/wolfHAL/watchdog/stm32f3_iwdg.h @@ -50,4 +50,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32f3_Iwdg_Cfg; #define WHAL_STM32F3_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 #define WHAL_STM32F3_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 +/* Config initializer macro alias. The F3 board.h supplies the body under + * the F3-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32F3_IWDG_DEV + #endif /* WHAL_STM32F3_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32f3_wwdg.h b/wolfHAL/watchdog/stm32f3_wwdg.h index 28ef983..a93a069 100644 --- a/wolfHAL/watchdog/stm32f3_wwdg.h +++ b/wolfHAL/watchdog/stm32f3_wwdg.h @@ -43,4 +43,8 @@ typedef whal_Stm32f0_Wwdg_Cfg whal_Stm32f3_Wwdg_Cfg; #define whal_Stm32f3_Wwdg_Refresh whal_Stm32f0_Wwdg_Refresh #endif /* !WHAL_CFG_STM32F3_WWDG_DIRECT_API_MAPPING */ +/* Config initializer macro alias. The F3 board.h supplies the body under + * the F3-prefixed name; the F0 driver source consumes the F0 name. */ +#define WHAL_CFG_STM32F0_WWDG_DEV WHAL_CFG_STM32F3_WWDG_DEV + #endif /* WHAL_STM32F3_WWDG_H */ diff --git a/wolfHAL/watchdog/stm32l1_iwdg.h b/wolfHAL/watchdog/stm32l1_iwdg.h index d50455a..053958e 100644 --- a/wolfHAL/watchdog/stm32l1_iwdg.h +++ b/wolfHAL/watchdog/stm32l1_iwdg.h @@ -50,4 +50,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32l1_Iwdg_Cfg; #define WHAL_STM32L1_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 #define WHAL_STM32L1_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 +/* Config initializer macro alias. The L1 board.h supplies the body under + * the L1-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32L1_IWDG_DEV + #endif /* WHAL_STM32L1_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32l1_wwdg.h b/wolfHAL/watchdog/stm32l1_wwdg.h index 25adb28..c64a988 100644 --- a/wolfHAL/watchdog/stm32l1_wwdg.h +++ b/wolfHAL/watchdog/stm32l1_wwdg.h @@ -43,4 +43,8 @@ typedef whal_Stm32f0_Wwdg_Cfg whal_Stm32l1_Wwdg_Cfg; #define whal_Stm32l1_Wwdg_Refresh whal_Stm32f0_Wwdg_Refresh #endif /* !WHAL_CFG_STM32L1_WWDG_DIRECT_API_MAPPING */ +/* Config initializer macro alias. The L1 board.h supplies the body under + * the L1-prefixed name; the F0 driver source consumes the F0 name. */ +#define WHAL_CFG_STM32F0_WWDG_DEV WHAL_CFG_STM32L1_WWDG_DEV + #endif /* WHAL_STM32L1_WWDG_H */ diff --git a/wolfHAL/watchdog/stm32n6_iwdg.h b/wolfHAL/watchdog/stm32n6_iwdg.h index 7d36150..87fec38 100644 --- a/wolfHAL/watchdog/stm32n6_iwdg.h +++ b/wolfHAL/watchdog/stm32n6_iwdg.h @@ -52,4 +52,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32n6_Iwdg_Cfg; #define WHAL_STM32N6_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 #define WHAL_STM32N6_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 +/* Config initializer macro alias. The N6 board.h supplies the body under + * the N6-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32N6_IWDG_DEV + #endif /* WHAL_STM32N6_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32n6_wwdg.h b/wolfHAL/watchdog/stm32n6_wwdg.h index b54ff48..64a738b 100644 --- a/wolfHAL/watchdog/stm32n6_wwdg.h +++ b/wolfHAL/watchdog/stm32n6_wwdg.h @@ -53,4 +53,8 @@ typedef whal_Stm32wb_Wwdg_Cfg whal_Stm32n6_Wwdg_Cfg; #define WHAL_STM32N6_WWDG_TB_64 WHAL_STM32WB_WWDG_TB_64 #define WHAL_STM32N6_WWDG_TB_128 WHAL_STM32WB_WWDG_TB_128 +/* Config initializer macro alias. The N6 board.h supplies the body under + * the N6-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_WWDG_DEV WHAL_CFG_STM32N6_WWDG_DEV + #endif /* WHAL_STM32N6_WWDG_H */ diff --git a/wolfHAL/watchdog/stm32u5_iwdg.h b/wolfHAL/watchdog/stm32u5_iwdg.h new file mode 100644 index 0000000..b4f4c1a --- /dev/null +++ b/wolfHAL/watchdog/stm32u5_iwdg.h @@ -0,0 +1,62 @@ +/* stm32u5_iwdg.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_IWDG_H +#define WHAL_STM32U5_IWDG_H + +/** + * @file stm32u5_iwdg.h + * @brief STM32U5 IWDG driver (alias for STM32WB IWDG). + * + * The STM32U5 IWDG peripheral is register-compatible with the STM32WB IWDG. + * This header re-exports the STM32WB IWDG driver types and symbols under + * STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32u5_Iwdg_Cfg; + +#define whal_Stm32u5_Iwdg_Dev whal_Stm32wb_Iwdg_Dev + +#ifndef WHAL_CFG_STM32U5_IWDG_DIRECT_API_MAPPING +#define whal_Stm32u5_Iwdg_Driver whal_Stm32wb_Iwdg_Driver +#define whal_Stm32u5_Iwdg_Init whal_Stm32wb_Iwdg_Init +#define whal_Stm32u5_Iwdg_Deinit whal_Stm32wb_Iwdg_Deinit +#define whal_Stm32u5_Iwdg_Refresh whal_Stm32wb_Iwdg_Refresh +#endif /* !WHAL_CFG_STM32U5_IWDG_DIRECT_API_MAPPING */ + +/** + * @brief Prescaler values (re-exported from STM32WB). + */ +#define WHAL_STM32U5_IWDG_PR_4 WHAL_STM32WB_IWDG_PR_4 +#define WHAL_STM32U5_IWDG_PR_8 WHAL_STM32WB_IWDG_PR_8 +#define WHAL_STM32U5_IWDG_PR_16 WHAL_STM32WB_IWDG_PR_16 +#define WHAL_STM32U5_IWDG_PR_32 WHAL_STM32WB_IWDG_PR_32 +#define WHAL_STM32U5_IWDG_PR_64 WHAL_STM32WB_IWDG_PR_64 +#define WHAL_STM32U5_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 +#define WHAL_STM32U5_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 + +/* Config initializer macro alias. The U5 board.h supplies the body under + * the U5-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32U5_IWDG_DEV + +#endif /* WHAL_STM32U5_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32u5_wwdg.h b/wolfHAL/watchdog/stm32u5_wwdg.h new file mode 100644 index 0000000..b6cb117 --- /dev/null +++ b/wolfHAL/watchdog/stm32u5_wwdg.h @@ -0,0 +1,63 @@ +/* stm32u5_wwdg.h + * + * Copyright (C) 2026 wolfSSL Inc. + * + * This file is part of wolfHAL. + * + * wolfHAL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * wolfHAL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA + */ + +#ifndef WHAL_STM32U5_WWDG_H +#define WHAL_STM32U5_WWDG_H + +/** + * @file stm32u5_wwdg.h + * @brief STM32U5 WWDG driver (alias for STM32WB WWDG). + * + * The STM32U5 WWDG peripheral is register-compatible with the STM32WB WWDG. + * This header re-exports the STM32WB WWDG driver types and symbols under + * STM32U5-specific names. + */ + +#include + +typedef whal_Stm32wb_Wwdg_Cfg whal_Stm32u5_Wwdg_Cfg; + +#define whal_Stm32u5_Wwdg_Dev whal_Stm32wb_Wwdg_Dev + +#ifndef WHAL_CFG_STM32U5_WWDG_DIRECT_API_MAPPING +#define whal_Stm32u5_Wwdg_Driver whal_Stm32wb_Wwdg_Driver +#define whal_Stm32u5_Wwdg_Init whal_Stm32wb_Wwdg_Init +#define whal_Stm32u5_Wwdg_Deinit whal_Stm32wb_Wwdg_Deinit +#define whal_Stm32u5_Wwdg_Refresh whal_Stm32wb_Wwdg_Refresh +#endif /* !WHAL_CFG_STM32U5_WWDG_DIRECT_API_MAPPING */ + +/** + * @brief Timebase prescaler values (re-exported from STM32WB). + */ +#define WHAL_STM32U5_WWDG_TB_1 WHAL_STM32WB_WWDG_TB_1 +#define WHAL_STM32U5_WWDG_TB_2 WHAL_STM32WB_WWDG_TB_2 +#define WHAL_STM32U5_WWDG_TB_4 WHAL_STM32WB_WWDG_TB_4 +#define WHAL_STM32U5_WWDG_TB_8 WHAL_STM32WB_WWDG_TB_8 +#define WHAL_STM32U5_WWDG_TB_16 WHAL_STM32WB_WWDG_TB_16 +#define WHAL_STM32U5_WWDG_TB_32 WHAL_STM32WB_WWDG_TB_32 +#define WHAL_STM32U5_WWDG_TB_64 WHAL_STM32WB_WWDG_TB_64 +#define WHAL_STM32U5_WWDG_TB_128 WHAL_STM32WB_WWDG_TB_128 + +/* Config initializer macro alias. The U5 board.h supplies the body under + * the U5-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_WWDG_DEV WHAL_CFG_STM32U5_WWDG_DEV + +#endif /* WHAL_STM32U5_WWDG_H */ diff --git a/wolfHAL/watchdog/stm32wba_iwdg.h b/wolfHAL/watchdog/stm32wba_iwdg.h index 5434c53..32383bf 100644 --- a/wolfHAL/watchdog/stm32wba_iwdg.h +++ b/wolfHAL/watchdog/stm32wba_iwdg.h @@ -55,4 +55,8 @@ typedef whal_Stm32wb_Iwdg_Cfg whal_Stm32wba_Iwdg_Cfg; #define WHAL_STM32WBA_IWDG_PR_128 WHAL_STM32WB_IWDG_PR_128 #define WHAL_STM32WBA_IWDG_PR_256 WHAL_STM32WB_IWDG_PR_256 +/* Config initializer macro alias. The WBA board.h supplies the body under + * the WBA-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_IWDG_DEV WHAL_CFG_STM32WBA_IWDG_DEV + #endif /* WHAL_STM32WBA_IWDG_H */ diff --git a/wolfHAL/watchdog/stm32wba_wwdg.h b/wolfHAL/watchdog/stm32wba_wwdg.h index 5ab1fb1..5c8b2d3 100644 --- a/wolfHAL/watchdog/stm32wba_wwdg.h +++ b/wolfHAL/watchdog/stm32wba_wwdg.h @@ -56,4 +56,8 @@ typedef whal_Stm32wb_Wwdg_Cfg whal_Stm32wba_Wwdg_Cfg; #define WHAL_STM32WBA_WWDG_TB_64 WHAL_STM32WB_WWDG_TB_64 #define WHAL_STM32WBA_WWDG_TB_128 WHAL_STM32WB_WWDG_TB_128 +/* Config initializer macro alias. The WBA board.h supplies the body under + * the WBA-prefixed name; the WB driver source consumes the WB name. */ +#define WHAL_CFG_STM32WB_WWDG_DEV WHAL_CFG_STM32WBA_WWDG_DEV + #endif /* WHAL_STM32WBA_WWDG_H */