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The FPGA can be made to execute on different conditions.
+ As default, it will execute if one of the inputs changes, or if it has a timed gate (as marked by red) inside it.
+ It should be noted that if 2 different inputs change the same tick, the FPGA will execute twice,
+ where the first execution will be with an old value for one of the inputs. This is due to how Wiremod works, where only one input is triggered at a time.
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+ To further customize chip execution, there are 3 different ways a chip can trigger an execution.
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Inputs
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+ The chip executes when an input is changed, and propagates the changes inside it, updating the gates affected by the input change.
+ Gates that aren't affected by the input change, will not execute.
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Timed
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+ Timed execution only affects gates which are timed (marked by red).
+ This includes gates such as 'OS Time' and 'Entity Position', which share the property that their output is time dependant.
+ For these gates to always have the correct output, timed execution needs to be on.
+ The frequency that these timed gates are updated with can be controlled with the Execution Interval setting.
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Trigger In
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+ For the greatest control over executions, the other options can be turned off and this one turned on.
+ The gate will get a "Trigger" input, which when set to something other than 0, will cause the chip to execute everything necessary.
+ The FPGA keeps a "lazy queue", such that it knows which gates will need to execute when the "Trigger" input is triggered.
+ This includes all timed gates, and input gates which have had their value changed since last trigger.
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Special execution gates
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+ To further customize how a chip executes, some special execution gates have been included.
+ They can be found under FPGA/Execution
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Execution Delta
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+ This chip will return the time between the current execution and the last one.
+ Useful for time critical circuitry - such as levitating - or calculations where the time difference is required.
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Execution Count
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+ Increments by one each time the chip executes
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Last (Normal/Vector/Angle/String)
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+ Mainly designed to allow looping circuitry. For example, a memory gate feeding it's own value + 1 into itself will produce an infinite loop.
+ If a Last gate is put somewhere in the loop, it will allow it to be executed. It does this by using the value the gate connected to it's input had last execution,
+ 'disengaging' the infinite loop.
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Previous (Normal/Vector/Angle/String)
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+ An alternative to the Last gate, that functions a bit differently. This gate will output the value the connected gate had the previous tick,
+ which differs from the Last gate behaviour both because multiple executions can happen each tick, which will cause the Last gate to change, but not the Previous gate.
+ The most important difference, is that the Previous gate will trigger a new execution during next tick, with the updated value.
+ This can cause a chain reaction, if this execution changes the Previous gate, causing it to trigger next tick again.
+ To avoid such chain reactions, the value should somehow stabilize - but the internal circuitry decides that.
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Last Timed (Normal/Vector/Angle/String)
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+ Alternative form of the Last gate, this one can trigger an execute if the FPGA is set to trigger on Timed.
+ This is useful for loops that are meant to execute every Execution Interval, where you don't care if the value has actually changed or not.
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