Merge branch 'master' of github.com:kksweet8845/rv32emu

Author: f74064054@mail.ncku.edu.tw

README.md

@@ -1,4 +1,4 @@
-# RISC-V RV32I[MA] emulator with ELF support
+# RISC-V RV32I[MAC] emulator with ELF support
 
 Emulator was originally created by Fabrice Bellard and then modified and shared on Hackaday by Frank Buss
 as a single C-file. Shaos added some additional statistics and macros.
@@ -12,20 +12,20 @@ How to compile it:
 ```shell
 $ gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i
 ```
+or
+```shell
+$ make emu-rv32i
+```
 
 Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance
+- Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/)
 ```shell
 $ make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant
 ```
 
 Compiling and running simple code:
 ```shell
-$ riscv32-unknown-elf-gcc -O3 -nostdlib test1.c -o test1
-```
-
-or
-```shell
-$ riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib test1.c -o test1
+$ make test1
 ```
 
 then
@@ -34,8 +34,17 @@ $ ./emu-rv32i test1
 Hello RISC-V!
 ```
 
-RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`.
+- RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`.
+
+
+Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance
+```shell
+make C-ADDI.log
+```
+If there is no accident, it will output the `TEST PASSED`
+
 
+- RV32C instructions can be enabled by commenting `#define RV32C`
 ## How to build RISC-V toolchain from scratch
 
 https://github.com/riscv/riscv-gnu-toolchain