Inter save

Author: f74064054@mail.ncku.edu.tw

CSRs.h

@@ -89,3 +89,91 @@ uint32_t uip;                /* User interrupt pending */
 // ====================================================== //
 uint32_t fflags;             /* Floating-Point Accrued Exceptions*/
 uint32_t frm;                /* Floating-Point Dynamic Rounding Mode*/
+uint32_t fcsr;               /* Floating-Point Control and Status Register (frm + fflags )*/
+// ====================================================== //
+// ================ User Counter / TImers =============== //
+// ====================================================== //
+uint32_t cycle;              /* Cycle counter for RDCYCLE instruction */
+uint32_t time;               /* Timer for RDTIME instruction */
+uint32_t instret;            /* Instructions-retired counter for RDINSTRET instructions*/
+uint32_t cycleh;             /* Upper 32 bits of cycle, RV32I only. */
+uint32_t timeh;              /* Upper 32 bits of time, RV32I only. */
+
+
+// ====================================================== //
+// ================ Supervior Trap Setup ================ //
+// ====================================================== //
+uint32_t sstatus;            /* Supervisor status register */
+uint32_t sedeleg;            /* Supervisor exception delegation register */
+uint32_t sideleg;            /* Supervisor interrupt delegation register */
+uint32_t sie;                /* Supervisor interrupt-enable register*/
+uint32_t stvec;              /* Supervisor trap handler base address */
+// ====================================================== //
+// ============== Supervisor Trap Handling ============== //
+// ====================================================== //
+uint32_t sscratch;          /* Scratch register for supervisor trap handlers */
+uint32_t sepc;              /* Supervisor exception program counter */
+uint32_t scause;            /* Supervisor trap cause */
+uint32_t sbadaddr;          /* Supervisor bad address */
+uint32_t sip;               /* Supervisor interrupt pending */
+// ====================================================== //
+// ======== Supervisor Protection and Translation ======= //
+// ====================================================== //
+uint32_t sptbr;             /* Page-table base register */
+
+
+// ====================================================== //
+// ================ Hypervisor Trap Setup =============== //
+// ====================================================== //
+uint32_t hstatus;           /* Hypervisor status register */
+uint32_t hedeleg;           /* Hypervisor exception delegation register */
+uint32_t hideleg;           /* Hyperbisor interrupt delegation register */
+uint32_t hie;               /* Hypervisor interrupt-enable register */
+uint32_t htvec;             /* Hypervisor trap handler base address */
+// ====================================================== //
+// ============== Hypervisor Trap Handling ============== //
+// ====================================================== //
+uint32_t hscratch;           /* Scratch register for hypervisor trap handlers */
+uint32_t hepc;               /* Hypervisor exception program counter */
+uint32_t hcause;             /* Hypervisor trap cause */
+uint32_t hbadaddr;           /* Hypervisor bad address */
+uint32_t hip;                /* Hypervisor interrupt pending */
+// ====================================================== //
+// ======== Hypervisor Protection and Translation ======= //
+// ====================================================== //
+// uint32_t TBD;                /* TBD */
+
+
+// ====================================================== //
+// ============ Machine Information Register ============ //
+// ====================================================== //
+uint32_t mvendorid;           /* Vendor ID*/
+uint32_t marchid;             /* Architecture ID */
+uint32_t mimpid;              /* Implementation ID */
+uint32_t mhartid;             /* Hardware thread ID */
+// ====================================================== //
+// ================= Machine Trap Setup ================= //
+// ====================================================== //
+uint32_t mstatus;             /* Machine status register */
+uint32_t misa;                /* ISA and extensions */
+uint32_t medeleg;             /* Machine exception delegation register */
+uint32_t mideleg;             /* Machine interrupt delegation register */
+uint32_t mie;                 /* Machine interrupt-enable register */
+uint32_t mtvec;               /* Machine trap-handler base address */
+// ====================================================== //
+// ================ Machine Trap Handling =============== //
+// ====================================================== //
+uint32_t mscratch;            /* Scratch register for machine trap handlers */
+uint32_t mepc;                /* Machine exception program counter */
+uint32_t mcause;              /* Machine trap cause */
+uint32_t mbadaddr;            /* Machine bad address */
+uint32_t mip;                 /* Machine interrupt pending */
+// ====================================================== //
+// ========= Machine Protextion and Translation ========= //
+// ====================================================== //
+uint32_t mbase;               /* Base regsiter */
+uint32_t mbound;              /* Bound register */
+uint32_t mibase;              /* Instruction base register */
+uint32_t mibound;             /* Instruction bound register */
+uint32_t mdbase;              /* Data base register */
+uint32_t mdbound;             /* Data bound register */

Makefile

@@ -6,14 +6,22 @@ RV32I_CFLAGS = -march=rv32i -mabi=ilp32 -O3 -nostdlib
 CFLAGS = -O3 -Wall
 LDFLAGS = -lelf
 
+RUN_TARGET := ./emu-rv32i
+WORK_DIR = work/rv32imc
+
+
 all: $(BINS)
-	
+
 emu-rv32i: emu-rv32i.c
 	$(CC) $(CFLAGS) -o $@ $< $(LDFLAGS)
 
 test1: test1.c
 	$(CROSS_COMPILE)gcc $(RV32I_CFLAGS) -o $@ $<
 
+
+%.log: $(WORK_DIR)/%.elf
+	$(RUN_TARGET) $<
+
 check: $(BINS)
 	./emu-rv32i test1
 

emu-rv32i.c

@@ -87,10 +87,10 @@ original copyright:
 #include <gelf.h>
 
 /* uncomment this for an instruction trace and other debug outputs */
-#if 0
+#if 1
 #define DEBUG_OUTPUT
 #endif
-#if 0
+#if 1
 #define DEBUG_EXTRA
 #endif
 
@@ -779,6 +779,8 @@ uint32_t get_insn32(uint32_t pc)
     uint32_t ptr = pc - ram_start;
     if (ptr > RAM_SIZE) return 1;
     uint8_t* p = ram + ptr;
+    if((p[0] & 0x03) < 3)
+        return p[0] | (p[1] << 8);
     return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
 }
 
@@ -1904,7 +1906,13 @@ void execute_instruction()
         break;
 
 #endif
+#ifndef RV32C
+
+    case 1: /* Compressed insn */
+
+        break;
 
+#endif
     default:
         raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn);
         return;
@@ -1944,6 +1952,9 @@ void riscv_cpu_interp_x32()
         } else {
             /* normal instruction execution */
             insn = get_insn32(pc);
+#ifdef DEBUG_EXTRA
+            printf("insn : %#x\n", insn);
+#endif
             insn_counter++;
 
 #ifdef DEBUG_OUTPUT
@@ -2023,7 +2034,7 @@ int main(int argc, char** argv)
                 GElf_Sym sym;
                 gelf_getsym(data, i, &sym);
                 char* name = elf_strptr(elf, shdr.sh_link, sym.st_name);
-#if 0
+#ifdef DEBUG_EXTRA
                 if(*name) printf("sym '%s' %lx\n",name,sym.st_value);
 #endif
                 if (strcmp(name, "begin_signature") == 0) {
@@ -2056,6 +2067,7 @@ int main(int argc, char** argv)
 
     /* scan for program */
     while ((scn = elf_nextscn(elf, scn)) != NULL) {
+        /* ELF Section Header Table*/
         gelf_getshdr(scn, &shdr);
         if (shdr.sh_type == SHT_PROGBITS) {
             Elf_Data *data = elf_getdata(scn, NULL);
@@ -2145,7 +2157,7 @@ int main(int argc, char** argv)
     /* run program in emulator */
     pc = ram_start;
     /* Initialize the address of stack pointer*/
-    reg[2] = ram_start + RAM_SIZE - 4;
+    reg[2] = ram_start + RAM_SIZE;
     riscv_cpu_interp_x32();
 
     uint64_t ns2 = get_clock();

include/RV32C-01.h

@@ -0,0 +1,6 @@
+#ifndef RV32C_H
+#define RC32C_H
+
+
+
+#endif