From 43cdcebc8a47898f4339e18d5cc51f56f51e63d0 Mon Sep 17 00:00:00 2001 From: Waffle Lapkin Date: Fri, 3 Apr 2026 21:07:17 +0200 Subject: [PATCH 01/15] rename `drop_in_place` lang item to `drop_glue` --- example/mini_core.rs | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/example/mini_core.rs b/example/mini_core.rs index 481fe5387e1..2d5a29ceb81 100644 --- a/example/mini_core.rs +++ b/example/mini_core.rs @@ -577,12 +577,10 @@ fn eh_personality() -> ! { loop {} } -#[lang = "drop_in_place"] -#[allow(unconditional_recursion)] -pub unsafe fn drop_in_place(to_drop: *mut T) { +#[lang = "drop_glue"] +pub unsafe fn drop_glue(_to_drop: &mut T) { // Code here does not matter - this is replaced by the // real drop glue by the compiler. - drop_in_place(to_drop); } #[lang = "unpin"] From d2a379f94afa9ce32ab7215bddef0e938248b7c5 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Wed, 4 Mar 2026 11:23:52 +0000 Subject: [PATCH 02/15] Move CrateInfo computation after codegen_crate CrateInfo is only necessary during linking and non-local LTO. --- src/lib.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 4be25b3fb09..6ca2ef88ef2 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -291,8 +291,8 @@ impl CodegenBackend for GccCodegenBackend { target_cpu(sess).to_owned() } - fn codegen_crate(&self, tcx: TyCtxt<'_>, crate_info: &CrateInfo) -> Box { - Box::new(codegen_crate(self.clone(), tcx, crate_info)) + fn codegen_crate(&self, tcx: TyCtxt<'_>) -> Box { + Box::new(codegen_crate(self.clone(), tcx)) } fn join_codegen( @@ -300,11 +300,12 @@ impl CodegenBackend for GccCodegenBackend { ongoing_codegen: Box, sess: &Session, _outputs: &OutputFilenames, + crate_info: &CrateInfo, ) -> (CompiledModules, FxIndexMap) { ongoing_codegen .downcast::>() .expect("Expected GccCodegenBackend's OngoingCodegen, found Box") - .join(sess) + .join(sess, crate_info) } fn target_config(&self, sess: &Session) -> TargetConfig { From 3ce0567a426be2c95241145965045eb04d572c76 Mon Sep 17 00:00:00 2001 From: bjorn3 <17426603+bjorn3@users.noreply.github.com> Date: Wed, 6 May 2026 14:18:13 +0000 Subject: [PATCH 03/15] Move invocation_temp into OutputFilenames While it was previously defined in Session, it is only ever used with OutputFilenames methods. --- src/back/write.rs | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/src/back/write.rs b/src/back/write.rs index 64674423de2..8fd38a2efd6 100644 --- a/src/back/write.rs +++ b/src/back/write.rs @@ -29,16 +29,8 @@ pub(crate) fn codegen( let lto_mode = module.module_llvm.lto_mode; let lto_supported = module.module_llvm.lto_supported; - let bc_out = cgcx.output_filenames.temp_path_for_cgu( - OutputType::Bitcode, - &module.name, - cgcx.invocation_temp.as_deref(), - ); - let obj_out = cgcx.output_filenames.temp_path_for_cgu( - OutputType::Object, - &module.name, - cgcx.invocation_temp.as_deref(), - ); + let bc_out = cgcx.output_filenames.temp_path_for_cgu(OutputType::Bitcode, &module.name); + let obj_out = cgcx.output_filenames.temp_path_for_cgu(OutputType::Object, &module.name); if config.bitcode_needed() { let _timer = @@ -82,22 +74,15 @@ pub(crate) fn codegen( } if config.emit_ir { - let out = cgcx.output_filenames.temp_path_for_cgu( - OutputType::LlvmAssembly, - &module.name, - cgcx.invocation_temp.as_deref(), - ); + let out = + cgcx.output_filenames.temp_path_for_cgu(OutputType::LlvmAssembly, &module.name); std::fs::write(out, "").expect("write file"); } if config.emit_asm { let _timer = prof.generic_activity_with_arg("GCC_module_codegen_emit_asm", &*module.name); - let path = cgcx.output_filenames.temp_path_for_cgu( - OutputType::Assembly, - &module.name, - cgcx.invocation_temp.as_deref(), - ); + let path = cgcx.output_filenames.temp_path_for_cgu(OutputType::Assembly, &module.name); context.compile_to_file(OutputKind::Assembler, path.to_str().expect("path to str")); } @@ -215,7 +200,6 @@ pub(crate) fn codegen( config.emit_asm, config.emit_ir, &cgcx.output_filenames, - cgcx.invocation_temp.as_deref(), ) } From 6f525503efbc1cbeb485a9375db856bf57f0747c Mon Sep 17 00:00:00 2001 From: Dirkjan Ochtman Date: Sun, 26 Apr 2026 12:09:05 +0200 Subject: [PATCH 04/15] Add Swift function call ABI Adds an unstable `extern "Swift"` ABI behind the `abi_swift` feature gate, mapping to LLVM's `swiftcc` calling convention. Cranelift and GCC backends fall back to the platform default since they have no equivalent. --- src/abi.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/abi.rs b/src/abi.rs index 2f5c555b702..7239a5bcb04 100644 --- a/src/abi.rs +++ b/src/abi.rs @@ -245,6 +245,8 @@ pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &Arch) -> Option return None, + // gcc/gccjit does not have anything for Swift's calling convention. + CanonAbi::Swift => panic!("gcc/gccjit backend does not support Swift calling convention"), CanonAbi::Arm(arm_call) => match arm_call { ArmCall::CCmseNonSecureCall => FnAttribute::ArmCmseNonsecureCall, ArmCall::CCmseNonSecureEntry => FnAttribute::ArmCmseNonsecureEntry, From 2f4c35e1582a675488b1d3f0b2ac83ac16170e64 Mon Sep 17 00:00:00 2001 From: khyperia <953151+khyperia@users.noreply.github.com> Date: Wed, 6 May 2026 09:32:56 +0200 Subject: [PATCH 05/15] Unnormalized migration: struct_tail takes fn taking Unnormalized --- src/intrinsic/simd.rs | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index a32592b45e5..ff5155f9f77 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -16,7 +16,7 @@ use rustc_codegen_ssa::traits::{BaseTypeCodegenMethods, BuilderMethods}; use rustc_hir as hir; use rustc_middle::mir::BinOp; use rustc_middle::ty::layout::HasTyCtxt; -use rustc_middle::ty::{self, Ty, Unnormalized}; +use rustc_middle::ty::{self, Ty}; use rustc_span::{Span, Symbol, sym}; use crate::builder::Builder; @@ -539,10 +539,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( match *in_elem.kind() { ty::RawPtr(p_ty, _) => { let metadata = p_ty.ptr_metadata_ty(bx.tcx, |ty| { - bx.tcx.normalize_erasing_regions( - ty::TypingEnv::fully_monomorphized(), - Unnormalized::new_wip(ty), - ) + bx.tcx.normalize_erasing_regions(ty::TypingEnv::fully_monomorphized(), ty) }); require!( metadata.is_unit(), @@ -556,10 +553,7 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( match *out_elem.kind() { ty::RawPtr(p_ty, _) => { let metadata = p_ty.ptr_metadata_ty(bx.tcx, |ty| { - bx.tcx.normalize_erasing_regions( - ty::TypingEnv::fully_monomorphized(), - Unnormalized::new_wip(ty), - ) + bx.tcx.normalize_erasing_regions(ty::TypingEnv::fully_monomorphized(), ty) }); require!( metadata.is_unit(), From 8474bb0758bad292de97d6c87b74c2e7da1b81ac Mon Sep 17 00:00:00 2001 From: Ian McCormack Date: Thu, 30 Apr 2026 19:49:04 -0400 Subject: [PATCH 06/15] Add trait methods for experimental retags to cg. --- src/intrinsic/mod.rs | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index d823e209fd7..6fb25174bf1 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -6,7 +6,6 @@ use std::iter; use gccjit::{ComparisonOp, Function, FunctionType, RValue, ToRValue, Type, UnaryOp}; use rustc_abi::{BackendRepr, HasDataLayout, WrappingRange}; -use rustc_codegen_ssa::MemFlags; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::common::IntPredicate; use rustc_codegen_ssa::errors::InvalidMonomorphization; @@ -18,6 +17,7 @@ use rustc_codegen_ssa::traits::{ ArgAbiBuilderMethods, BaseTypeCodegenMethods, BuilderMethods, ConstCodegenMethods, IntrinsicCallBuilderMethods, LayoutTypeCodegenMethods, }; +use rustc_codegen_ssa::{MemFlags, RetagInfo}; use rustc_data_structures::fx::FxHashSet; #[cfg(feature = "master")] use rustc_middle::ty::layout::FnAbiOf; @@ -702,6 +702,14 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc // FIXME(antoyo): implement. self.context.new_rvalue_from_int(self.int_type, 0) } + + fn retag_reg(&mut self, _ptr: Self::Value, _info: &RetagInfo) -> Self::Value { + unimplemented!() + } + + fn retag_mem(&mut self, _ptr: Self::Value, _info: &RetagInfo) { + unimplemented!() + } } impl<'a, 'gcc, 'tcx> ArgAbiBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> { From 5e72aee9b8faeec262897c9a30d5576863fa9ae7 Mon Sep 17 00:00:00 2001 From: Scott McMurray Date: Sun, 3 May 2026 12:01:22 -0700 Subject: [PATCH 07/15] Let intrinsics use the SSA operand path --- src/context.rs | 6 +++++- src/intrinsic/mod.rs | 34 ++++++++++++++++++++-------------- src/intrinsic/simd.rs | 14 +++++++------- 3 files changed, 32 insertions(+), 22 deletions(-) diff --git a/src/context.rs b/src/context.rs index e0810a35b04..ed313859aea 100644 --- a/src/context.rs +++ b/src/context.rs @@ -19,7 +19,7 @@ use rustc_middle::ty::{self, ExistentialTraitRef, Instance, Ty, TyCtxt}; use rustc_session::Session; #[cfg(feature = "master")] use rustc_session::config::DebugInfo; -use rustc_span::{DUMMY_SP, Span, respan}; +use rustc_span::{DUMMY_SP, Span, Symbol, respan}; use rustc_target::spec::{HasTargetSpec, HasX86AbiOpt, Target, TlsModel, X86Abi}; #[cfg(feature = "master")] @@ -497,6 +497,10 @@ impl<'gcc, 'tcx> MiscCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> { None } } + + fn intrinsic_call_expects_place_always(&self, _name: Symbol) -> bool { + true + } } impl<'gcc, 'tcx> HasTyCtxt<'tcx> for CodegenCx<'gcc, 'tcx> { diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 6fb25174bf1..f56cec6ce22 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -9,6 +9,7 @@ use rustc_abi::{BackendRepr, HasDataLayout, WrappingRange}; use rustc_codegen_ssa::base::wants_msvc_seh; use rustc_codegen_ssa::common::IntPredicate; use rustc_codegen_ssa::errors::InvalidMonomorphization; +use rustc_codegen_ssa::mir::IntrinsicResult; use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue}; use rustc_codegen_ssa::mir::place::{PlaceRef, PlaceValue}; #[cfg(feature = "master")] @@ -194,11 +195,14 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc &mut self, instance: Instance<'tcx>, args: &[OperandRef<'tcx, RValue<'gcc>>], - result: PlaceRef<'tcx, RValue<'gcc>>, + result_layout: ty::layout::TyAndLayout<'tcx>, + result_place: Option>>, span: Span, - ) -> Result<(), Instance<'tcx>> { + ) -> IntrinsicResult<'tcx, RValue<'gcc>> { let tcx = self.tcx; + let result = PlaceRef { val: result_place.unwrap(), layout: result_layout }; + let name = tcx.item_name(instance.def_id()); let name_str = name.as_str(); let fn_args = instance.args; @@ -353,7 +357,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc args[2].immediate(), result, ); - return Ok(()); + return IntrinsicResult::WroteIntoPlace; } sym::breakpoint => { unimplemented!(); @@ -375,12 +379,12 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc sym::volatile_store => { let dst = args[0].deref(self.cx()); args[1].val.volatile_store(self, dst); - return Ok(()); + return IntrinsicResult::WroteIntoPlace; } sym::unaligned_volatile_store => { let dst = args[0].deref(self.cx()); args[1].val.unaligned_volatile_store(self, dst); - return Ok(()); + return IntrinsicResult::WroteIntoPlace; } sym::prefetch_read_data | sym::prefetch_write_data @@ -448,12 +452,12 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc _ => bug!(), }, None => { - tcx.dcx().emit_err(InvalidMonomorphization::BasicIntegerType { + let err = tcx.dcx().emit_err(InvalidMonomorphization::BasicIntegerType { span, name, ty: args[0].layout.ty, }); - return Ok(()); + return IntrinsicResult::Err(err); } } } @@ -544,7 +548,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc extended_asm.set_volatile_flag(true); // We have copied the value to `result` already. - return Ok(()); + return IntrinsicResult::WroteIntoPlace; } sym::ptr_mask => { @@ -569,12 +573,15 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc span, ) { Ok(value) => value, - Err(()) => return Ok(()), + Err(err) => return IntrinsicResult::Err(err), } } // Fall back to default body - _ => return Err(Instance::new_raw(instance.def_id(), instance.args)), + _ => { + let fallback = Instance::new_raw(instance.def_id(), instance.args); + return IntrinsicResult::Fallback(fallback); + } }; if result.layout.ty.is_bool() { @@ -583,7 +590,7 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc } else if !result.layout.ty.is_unit() { self.store_to_place(value, result.val); } - Ok(()) + IntrinsicResult::WroteIntoPlace } fn codegen_llvm_intrinsic_call( @@ -694,13 +701,12 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc self.context.new_rvalue_from_int(self.int_type, 0) } - fn va_start(&mut self, _va_list: RValue<'gcc>) -> RValue<'gcc> { + fn va_start(&mut self, _va_list: RValue<'gcc>) { unimplemented!(); } - fn va_end(&mut self, _va_list: RValue<'gcc>) -> RValue<'gcc> { + fn va_end(&mut self, _va_list: RValue<'gcc>) { // FIXME(antoyo): implement. - self.context.new_rvalue_from_int(self.int_type, 0) } fn retag_reg(&mut self, _ptr: Self::Value, _info: &RetagInfo) -> Self::Value { diff --git a/src/intrinsic/simd.rs b/src/intrinsic/simd.rs index ff5155f9f77..82ef99703b2 100644 --- a/src/intrinsic/simd.rs +++ b/src/intrinsic/simd.rs @@ -17,7 +17,7 @@ use rustc_hir as hir; use rustc_middle::mir::BinOp; use rustc_middle::ty::layout::HasTyCtxt; use rustc_middle::ty::{self, Ty}; -use rustc_span::{Span, Symbol, sym}; +use rustc_span::{ErrorGuaranteed, Span, Symbol, sym}; use crate::builder::Builder; #[cfg(not(feature = "master"))] @@ -32,12 +32,12 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( ret_ty: Ty<'tcx>, llret_ty: Type<'gcc>, span: Span, -) -> Result, ()> { +) -> Result, ErrorGuaranteed> { // macros for error handling: macro_rules! return_error { ($err:expr) => {{ - bx.tcx.dcx().emit_err($err); - return Err(()); + let err = bx.tcx.dcx().emit_err($err); + return Err(err); }}; } macro_rules! require { @@ -803,11 +803,11 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>( bx: &mut Builder<'_, 'gcc, 'tcx>, span: Span, args: &[OperandRef<'tcx, RValue<'gcc>>], - ) -> Result, ()> { + ) -> Result, ErrorGuaranteed> { macro_rules! return_error { ($err:expr) => {{ - bx.tcx.dcx().emit_err($err); - return Err(()); + let err = bx.tcx.dcx().emit_err($err); + return Err(err); }}; } let ty::Float(ref f) = *in_elem.kind() else { From 0a4077f57236a94a24a21658f718ab71671ae044 Mon Sep 17 00:00:00 2001 From: Guillaume Gomez Date: Sat, 23 May 2026 12:22:43 +0200 Subject: [PATCH 08/15] Fix invalid cg_gcc `panic` function cast --- src/intrinsic/mod.rs | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs index 6fb25174bf1..a244a9c493a 100644 --- a/src/intrinsic/mod.rs +++ b/src/intrinsic/mod.rs @@ -1352,7 +1352,10 @@ fn try_intrinsic<'a, 'b, 'gcc, 'tcx>( dest: PlaceRef<'tcx, RValue<'gcc>>, ) { if !bx.sess().panic_strategy().unwinds() { - bx.call(bx.type_void(), None, None, try_func, &[data], None, None); + let param_type = bx.u8_type.make_pointer(); + let fn_type = + bx.context.new_function_pointer_type(None, bx.type_void(), &[param_type], false); + bx.call(fn_type, None, None, try_func, &[data], None, None); // Return 0 unconditionally from the intrinsic call; // we can never unwind. OperandValue::Immediate(bx.const_i32(0)).store(bx, dest); From 2ad24e164046d5be695a21f41b48ce77228a8fd5 Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Sun, 10 May 2026 17:02:34 +0200 Subject: [PATCH 09/15] MIR inlining: allow backends to opt-in to inlining intrinsics --- src/lib.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index 6ca2ef88ef2..8e7611ed493 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -98,7 +98,7 @@ use rustc_middle::ty::TyCtxt; use rustc_middle::util::Providers; use rustc_session::Session; use rustc_session::config::{OptLevel, OutputFilenames}; -use rustc_span::Symbol; +use rustc_span::{Symbol, sym}; use rustc_target::spec::{Arch, RelocModel}; use tempfile::TempDir; @@ -311,6 +311,10 @@ impl CodegenBackend for GccCodegenBackend { fn target_config(&self, sess: &Session) -> TargetConfig { target_config(sess, &self.target_info) } + + fn fallback_intrinsics(&self) -> Vec { + vec![sym::type_id_eq] + } } fn new_context<'gcc, 'tcx>(tcx: TyCtxt<'tcx>) -> Context<'gcc> { From cf570452c6063e38f6246150a55e5d035963a617 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Thu, 28 May 2026 17:38:11 -0400 Subject: [PATCH 10/15] Update to nightly-2026-05-28 --- rust-toolchain | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust-toolchain b/rust-toolchain index 02c9b54898a..7860423093b 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1,3 +1,3 @@ [toolchain] -channel = "nightly-2026-05-06" +channel = "nightly-2026-05-28" components = ["rust-src", "rustc-dev", "llvm-tools-preview"] From 07ba76745bf660ef08c928a8336300934442b756 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 May 2026 07:53:23 -0400 Subject: [PATCH 11/15] Ignore spelling --- tools/cspell_dicts/rustc_codegen_gcc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/cspell_dicts/rustc_codegen_gcc.txt b/tools/cspell_dicts/rustc_codegen_gcc.txt index 4fb018b3ecd..619221d5260 100644 --- a/tools/cspell_dicts/rustc_codegen_gcc.txt +++ b/tools/cspell_dicts/rustc_codegen_gcc.txt @@ -60,6 +60,7 @@ nvptx pointee powitf reassoc +retag riscv rlib roundevenf From e2ae9ad50f4bca05878b39e1080b0795051b8d40 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 May 2026 09:00:32 -0400 Subject: [PATCH 12/15] Add missing LLVM intrinsic mapping --- src/intrinsic/llvm.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index d58697f1bf2..b7495e0e4c4 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -489,6 +489,19 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>( let minus_one = builder.context.new_rvalue_from_int(arg4_type, -1); args = vec![new_args[1], new_args[0], new_args[2], minus_one].into(); } + "__builtin_ia32_fpclassph128_mask" + | "__builtin_ia32_fpclassph256_mask" + | "__builtin_ia32_fpclassph512_mask" + | "__builtin_ia32_fpclasspd128_mask" + | "__builtin_ia32_fpclassps128_mask" + | "__builtin_ia32_fpclasspd256_mask" + | "__builtin_ia32_fpclassps256_mask" + | "__builtin_ia32_fpclasspd512_mask" => { + let new_args = args.to_vec(); + let arg3_type = gcc_func.get_param_type(2); + let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); + args = vec![new_args[0], new_args[1], minus_one].into(); + } "__builtin_ia32_xrstor" | "__builtin_ia32_xrstor64" | "__builtin_ia32_xsavec" @@ -1577,6 +1590,17 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.uitofp.round.v4f64.v4i64" => "__builtin_ia32_cvtuqq2pd256_mask", "llvm.x86.avx512.uitofp.round.v8f32.v8i64" => "__builtin_ia32_cvtuqq2ps512_mask", "llvm.x86.avx512.uitofp.round.v4f32.v4i64" => "__builtin_ia32_cvtuqq2ps256_mask", + "llvm.x86.avx512fp16.fpclass.ph.128" => "__builtin_ia32_fpclassph128_mask", + "llvm.x86.avx512fp16.mask.cmp.ph.128" => "__builtin_ia32_cmpph128_mask", + "llvm.x86.avx512fp16.fpclass.ph.256" => "__builtin_ia32_fpclassph256_mask", + "llvm.x86.avx512fp16.fpclass.ph.512" => "__builtin_ia32_fpclassph512_mask", + "llvm.x86.avx512fp16.mask.cmp.ph.256" => "__builtin_ia32_cmpph256_mask", + "llvm.x86.avx512fp16.mask.cmp.ph.512" => "__builtin_ia32_cmpph512_mask_round", + "llvm.x86.avx512.fpclass.pd.128" => "__builtin_ia32_fpclasspd128_mask", + "llvm.x86.avx512.fpclass.ps.128" => "__builtin_ia32_fpclassps128_mask", + "llvm.x86.avx512.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", + "llvm.x86.avx512.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", + "llvm.x86.avx512.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", // FIXME: support the tile builtins: "llvm.x86.ldtilecfg" => "__builtin_trap", From f775c8179b8c0fe717d8375daf382f1a42d499c9 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 May 2026 11:17:14 -0400 Subject: [PATCH 13/15] Add more missing LLVM intrinsic mapping --- src/builder.rs | 12 +++++++-- src/intrinsic/llvm.rs | 62 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 71 insertions(+), 3 deletions(-) diff --git a/src/builder.rs b/src/builder.rs index 33f0f6fc2f8..4a5fbfee2ca 100644 --- a/src/builder.rs +++ b/src/builder.rs @@ -418,8 +418,16 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> { self.location, self.cx.context.new_call_through_ptr(self.location, func_ptr, &args), ); - // Return dummy value when not having return value. - self.context.new_rvalue_zero(self.isize_type) + // Return dummy value when not having return value, unless the intrinsic adapter + // needs to synthesize a non-void LLVM-level result from out-parameters. + llvm::adjust_intrinsic_return_value( + self, + self.context.new_rvalue_zero(self.isize_type), + &func_name, + &args, + args_adjusted, + orig_args, + ) } } diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs index b7495e0e4c4..b19f63dd077 100644 --- a/src/intrinsic/llvm.rs +++ b/src/intrinsic/llvm.rs @@ -478,6 +478,26 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>( new_args.push(variable.get_address(None)); args = new_args.into(); } + "__builtin_ia32_2intersectd128" + | "__builtin_ia32_2intersectq128" + | "__builtin_ia32_2intersectd256" + | "__builtin_ia32_2intersectq256" + | "__builtin_ia32_2intersectd512" + | "__builtin_ia32_2intersectq512" => { + let old_args = args.to_vec(); + let mut new_args = vec![]; + let arg1_type = gcc_func.get_param_type(0); + let first_mask = + builder.current_func().new_local(None, arg1_type, "return_2intersect_arg1"); + let arg2_type = gcc_func.get_param_type(1); + let second_mask = + builder.current_func().new_local(None, arg2_type, "return_2intersect_arg2"); + new_args.push(first_mask.get_address(None)); + new_args.push(second_mask.get_address(None)); + new_args.push(old_args[0]); + new_args.push(old_args[1]); + args = new_args.into(); + } "__builtin_ia32_vpermt2varqi512_mask" | "__builtin_ia32_vpermt2varqi256_mask" | "__builtin_ia32_vpermt2varqi128_mask" @@ -496,7 +516,11 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>( | "__builtin_ia32_fpclassps128_mask" | "__builtin_ia32_fpclasspd256_mask" | "__builtin_ia32_fpclassps256_mask" - | "__builtin_ia32_fpclasspd512_mask" => { + | "__builtin_ia32_fpclasspd512_mask" + | "__builtin_ia32_fpclassps512_mask" + | "__builtin_ia32_vpshufbitqmb128_mask" + | "__builtin_ia32_vpshufbitqmb256_mask" + | "__builtin_ia32_vpshufbitqmb512_mask" => { let new_args = args.to_vec(); let arg3_type = gcc_func.get_param_type(2); let minus_one = builder.context.new_rvalue_from_int(arg3_type, -1); @@ -867,6 +891,25 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>( &[random_number, success_variable.to_rvalue()], ); } + "__builtin_ia32_2intersectd128" + | "__builtin_ia32_2intersectq128" + | "__builtin_ia32_2intersectd256" + | "__builtin_ia32_2intersectq256" + | "__builtin_ia32_2intersectd512" + | "__builtin_ia32_2intersectq512" => { + let first_mask = args[0].dereference(None).to_rvalue(); + let second_mask = args[1].dereference(None).to_rvalue(); + let field1 = builder.context.new_field(None, first_mask.get_type(), "first_mask"); + let field2 = builder.context.new_field(None, second_mask.get_type(), "second_mask"); + let struct_type = + builder.context.new_struct_type(None, "vp2intersect_result", &[field1, field2]); + return_value = builder.context.new_struct_constructor( + None, + struct_type.as_type(), + None, + &[first_mask, second_mask], + ); + } "fma" => { let f16_type = builder.context.new_c_type(CType::Float16); return_value = builder.context.new_cast(None, return_value, f16_type); @@ -1195,6 +1238,9 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.mask.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask", "llvm.x86.avx512.mask.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask", "llvm.x86.avx512.mask.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask", + "llvm.x86.avx512.vpshufbitqmb.512" => "__builtin_ia32_vpshufbitqmb512_mask", + "llvm.x86.avx512.vpshufbitqmb.256" => "__builtin_ia32_vpshufbitqmb256_mask", + "llvm.x86.avx512.vpshufbitqmb.128" => "__builtin_ia32_vpshufbitqmb128_mask", "llvm.x86.avx512.mask.ucmp.w.512" => "__builtin_ia32_ucmpw512_mask", "llvm.x86.avx512.mask.ucmp.w.256" => "__builtin_ia32_ucmpw256_mask", "llvm.x86.avx512.mask.ucmp.w.128" => "__builtin_ia32_ucmpw128_mask", @@ -1352,11 +1398,20 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512bf16.cvtne2ps2bf16.128" => "__builtin_ia32_cvtne2ps2bf16_v8bf", "llvm.x86.avx512bf16.cvtne2ps2bf16.256" => "__builtin_ia32_cvtne2ps2bf16_v16bf", "llvm.x86.avx512bf16.cvtne2ps2bf16.512" => "__builtin_ia32_cvtne2ps2bf16_v32bf", + "llvm.x86.vcvtneps2bf16128" => "__builtin_ia32_cvtneps2bf16_v4sf", + "llvm.x86.vcvtneps2bf16256" => "__builtin_ia32_cvtneps2bf16_v8sf", + "llvm.x86.avx512bf16.mask.cvtneps2bf16.128" => "__builtin_ia32_cvtneps2bf16_v4sf_mask", "llvm.x86.avx512bf16.cvtneps2bf16.256" => "__builtin_ia32_cvtneps2bf16_v8sf", "llvm.x86.avx512bf16.cvtneps2bf16.512" => "__builtin_ia32_cvtneps2bf16_v16sf", "llvm.x86.avx512bf16.dpbf16ps.128" => "__builtin_ia32_dpbf16ps_v4sf", "llvm.x86.avx512bf16.dpbf16ps.256" => "__builtin_ia32_dpbf16ps_v8sf", "llvm.x86.avx512bf16.dpbf16ps.512" => "__builtin_ia32_dpbf16ps_v16sf", + "llvm.x86.avx512.vp2intersect.d.128" => "__builtin_ia32_2intersectd128", + "llvm.x86.avx512.vp2intersect.q.128" => "__builtin_ia32_2intersectq128", + "llvm.x86.avx512.vp2intersect.d.256" => "__builtin_ia32_2intersectd256", + "llvm.x86.avx512.vp2intersect.q.256" => "__builtin_ia32_2intersectq256", + "llvm.x86.avx512.vp2intersect.d.512" => "__builtin_ia32_2intersectd512", + "llvm.x86.avx512.vp2intersect.q.512" => "__builtin_ia32_2intersectq512", "llvm.x86.pclmulqdq.512" => "__builtin_ia32_vpclmulqdq_v8di", "llvm.x86.pclmulqdq.256" => "__builtin_ia32_vpclmulqdq_v4di", "llvm.x86.avx512.pmulhu.w.512" => "__builtin_ia32_pmulhuw512_mask", @@ -1601,6 +1656,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.avx512.fpclass.pd.256" => "__builtin_ia32_fpclasspd256_mask", "llvm.x86.avx512.fpclass.ps.256" => "__builtin_ia32_fpclassps256_mask", "llvm.x86.avx512.fpclass.pd.512" => "__builtin_ia32_fpclasspd512_mask", + "llvm.x86.avx512.fpclass.ps.512" => "__builtin_ia32_fpclassps512_mask", // FIXME: support the tile builtins: "llvm.x86.ldtilecfg" => "__builtin_trap", @@ -1631,6 +1687,10 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function "llvm.x86.tcvtrowd2psi" => "__builtin_trap", "llvm.x86.tcvtrowps2phhi" => "__builtin_trap", "llvm.x86.tcvtrowps2phli" => "__builtin_trap", + "llvm.x86.tcvtrowps2bf16h" => "__builtin_trap", + "llvm.x86.tcvtrowps2bf16hi" => "__builtin_trap", + "llvm.x86.tcvtrowps2bf16l" => "__builtin_trap", + "llvm.x86.tcvtrowps2bf16li" => "__builtin_trap", "llvm.x86.tcmmimfp16ps" => "__builtin_trap", "llvm.x86.tcmmrlfp16ps" => "__builtin_trap", From 5dad41cef0341db45fc8bf08bbd3723da6b2026d Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 May 2026 13:40:25 -0400 Subject: [PATCH 14/15] Update GCC version --- libgccjit.version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libgccjit.version b/libgccjit.version index 5eef7026046..104e5c7e2a0 100644 --- a/libgccjit.version +++ b/libgccjit.version @@ -1 +1 @@ -6f155cc3f5a2dff33afe6cc3ed6c2e0e605ae6a3 +d98bd412c7fb6bf8f2258e75f2e2b42f56a06bc1 From 86a4fa09969d349a7f6e688101809ed0d1ae6a56 Mon Sep 17 00:00:00 2001 From: Antoni Boucher Date: Fri, 29 May 2026 14:32:32 -0400 Subject: [PATCH 15/15] Add cpuid.def to enable the feature AVX512_VP2INTERSECT --- .github/workflows/stdarch.yml | 2 +- tests/cpuid.def | 62 +++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 tests/cpuid.def diff --git a/.github/workflows/stdarch.yml b/.github/workflows/stdarch.yml index 66f30b147b4..34438a097c6 100644 --- a/.github/workflows/stdarch.yml +++ b/.github/workflows/stdarch.yml @@ -21,7 +21,7 @@ jobs: fail-fast: false matrix: cargo_runner: [ - "sde -future -rtm_mode full --", + "sde -cpuid-in /home/runner/work/rustc_codegen_gcc/rustc_codegen_gcc/tests/cpuid.def -rtm_mode full --", "", ] diff --git a/tests/cpuid.def b/tests/cpuid.def new file mode 100644 index 00000000000..342f7d83a63 --- /dev/null +++ b/tests/cpuid.def @@ -0,0 +1,62 @@ +# Copyright (C) 2017-2025 Intel Corporation. +# +# This software and the related documents are Intel copyrighted materials, and your +# use of them is governed by the express license under which they were provided to +# you ("License"). Unless the License provides otherwise, you may not use, modify, +# copy, publish, distribute, disclose or transmit this software or the related +# documents without Intel's prior written permission. +# +# This software and the related documents are provided as is, with no express or +# implied warranties, other than those that are expressly stated in the License. +# +# CPUID_VERSION = 1.0 +# Input => Output +# EAX ECX => EAX EBX ECX EDX +00000000 ******** => 00000024 756e6547 6c65746e 49656e69 +00000001 ******** => 00400f10 00100800 7ffaf3ff bfebfbff +00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000 +00000003 ******** => 00000000 00000000 00000000 00000000 +00000004 00000000 => 7c004121 01c0003f 0000003f 00000000 #Deterministic Cache +00000004 00000001 => 7c004122 01c0003f 0000003f 00000000 +00000004 00000002 => 7c004143 03c0003f 000003ff 00000000 +00000004 00000003 => 7c0fc163 0280003f 0000dfff 00000004 +00000004 00000004 => 00000000 00000000 00000000 00000000 +00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT +00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power +00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features +00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e +00000008 ******** => 00000000 00000000 00000000 00000000 +00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache +0000000a ******** => 07300403 00000000 00000000 00000603 +0000000b 00000000 => 00000001 00000002 00000100 00000000 #Extended Topology +0000000b 00000001 => 00000004 00000002 00000201 00000000 +0000000c ******** => 00000000 00000000 00000000 00000000 +0000000d 00000000 => 000e02e7 00002b00 00002b00 00000000 #xcr0 +0000000d 00000001 => 0000001f 00000240 00000100 00000000 +0000000d 00000002 => 00000100 00000240 00000000 00000000 +0000000d 00000005 => 00000040 00000440 00000000 00000000 #zmasks +0000000d 00000006 => 00000200 00000480 00000000 00000000 #zmmh +0000000d 00000007 => 00000400 00000680 00000000 00000000 #zmm +0000000d 00000011 => 00000040 00000ac0 00000002 00000000 #tileconfig +0000000d 00000012 => 00002000 00000b00 00000006 00000000 #tiles +0000000d 00000013 => 00000080 000003c0 00000000 00000000 #APX +00000014 00000000 => 00000000 00000010 00000000 00000000 #ptwrite +00000019 ******** => 00000000 00000005 00000000 00000000 #Key Locker +0000001d 00000000 => 00000001 00000000 00000000 00000000 #AMX Tile +0000001d 00000001 => 04002000 00080040 00000010 00000000 #AMX Palette1 +0000001e 00000000 => 00000001 00004010 00000000 00000000 #AMX Tmul +0000001e 00000001 => 000001ff 00000000 00000000 00000000 +00000024 00000000 => 00000001 00070002 00000000 00000000 #AVX10 +00000024 00000001 => 00000000 00000000 00000004 00000000 +80000000 ******** => 80000008 00000000 00000000 00000000 +80000001 ******** => 00000000 00000000 00000121 2c100000 +80000002 ******** => 00000000 00000000 00000000 00000000 +80000003 ******** => 00000000 00000000 00000000 00000000 +80000004 ******** => 00000000 00000000 00000000 00000000 +80000005 ******** => 00000000 00000000 00000000 00000000 +80000006 ******** => 00000000 00000000 01006040 00000000 +80000007 ******** => 00000000 00000000 00000000 00000100 +80000008 ******** => 00003028 00000200 00000200 00000000 + +# This file was copied from intel-sde/misc/cpuid/future/cpuid.def, and modified to +# add support for `AVX512_VP2INTERSECT`