basic_usage.sv

/**
 * NeoRAM Basic Usage Example (Updated for v1.3.0)
 *
 * This example demonstrates how to instantiate and use the NeoRAM controller
 * in a simple design. Features proper ready signal handling and 32-bit data width.
 */
module neoram_example (
    input         clk,       // System clock
    input         rst_n,     // Active-low reset
    
    // User interface (example bus)
    input  [7:0]  addr_in,   // Address from user
    input  [31:0] data_in,   // Data from user
    input         write_req, // Write request
    input         read_req,  // Read request
    output [31:0] data_out,  // Data to user
    output        ready      // Operation complete
);

    // Internal signals
    logic [7:0]  neoram_addr;
    logic [31:0] neoram_write_data;
    logic        neoram_write_en;
    logic [31:0] neoram_read_data;
    logic        neoram_ready;
    logic        neoram_error;
    
    // Simple state machine to control the interface
    typedef enum {IDLE, WRITING, READING, WAIT_READY} state_t;
    state_t state, next_state;
    
    // State registers
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end
    
    // Next state logic
    always_comb begin
        next_state = state; // Default: stay in current state
        
        case (state)
            IDLE: begin
                if (write_req) begin
                    next_state = WRITING;
                end else if (read_req) begin
                    next_state = READING;
                end
            end
            
            WRITING, READING: begin
                next_state = WAIT_READY;
            end
            
            WAIT_READY: begin
                if (neoram_ready) begin
                    next_state = IDLE;
                end
            end
            
            default: next_state = IDLE;
        endcase
    end
    
    // Output logic
    always_comb begin
        // Default values
        neoram_addr = 8'd0;
        neoram_write_data = 32'd0;
        neoram_write_en = 1'b0;
        
        case (state)
            IDLE: begin
                // Idle state, no signals active
            end
            
            WRITING: begin
                neoram_addr = addr_in;
                neoram_write_data = data_in;
                neoram_write_en = 1'b1;
            end
            
            READING: begin
                neoram_addr = addr_in;
                neoram_write_en = 1'b0;
            end
            
            WAIT_READY: begin
                // Hold signals steady while waiting
                if (write_req) begin
                    neoram_addr = addr_in;
                    neoram_write_data = data_in;
                    neoram_write_en = 1'b1;
                end else if (read_req) begin
                    neoram_addr = addr_in;
                    neoram_write_en = 1'b0;
                end
            end
        endcase
    end
    
    // Output assignments
    assign data_out = neoram_read_data;
    assign ready = (state == IDLE);
    
    // Instantiate NeoRAM controller (single port configuration)
    neoram_controller #(
        .ADDR_WIDTH(8),       // 8-bit address
        .DATA_WIDTH(32),      // 32-bit data
        .NUM_PORTS(1)         // Single port for simplicity
    ) neoram_inst (
        .clk            (clk),
        .rst_n          (rst_n),
        .addr           (neoram_addr),      // Connect your address
        .write_data     (neoram_write_data), // Connect your write data
        .write_en       (neoram_write_en),   // Connect your write enable
        .read_data      (neoram_read_data),  // Connect to your read data output
        .ready          (neoram_ready),      // Connect to your ready signal
        .error          (neoram_error)       // Connect to error handling logic
    );
    
    // Error handling (optional)
    // Note: In v1.3.0, ready signals are properly initialized and error handling is improved
    always_ff @(posedge clk) begin
        if (neoram_error) begin
            // Log error or take appropriate action
            $display("NeoRAM Error detected at time %t", $time);
            // In ECC mode, single-bit errors are automatically corrected
            // Multi-bit errors will be flagged but data may be corrupted
        end
    end
    
    // Ready signal monitoring (v1.3.0 improvement)
    // The ready signal is now properly initialized and will not have 'x' states
    initial begin
        $display("NeoRAM Basic Usage Example - v1.3.0");
        $display("Features: 32-bit data width, proper ready signal initialization");
    end

endmodule