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update rt1050 sdk to version 2.8.5
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‎sdk/devices/MIMXRT1052/MIMXRT1052.h‎

Lines changed: 1701 additions & 53 deletions
Large diffs are not rendered by default.

‎sdk/devices/MIMXRT1052/MIMXRT1052.xml‎

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29556,6 +29556,78 @@ SPDX-License-Identifier: BSD-3-Clause
2955629556
</field>
2955729557
</fields>
2955829558
</register>
29559+
<register>
29560+
<name>USB1_LOOPBACK</name>
29561+
<description>USB Loopback Test Register</description>
29562+
<addressOffset>0x1E0</addressOffset>
29563+
<size>32</size>
29564+
<access>read-write</access>
29565+
<resetValue>0</resetValue>
29566+
<resetMask>0xFFFFFFFF</resetMask>
29567+
<fields>
29568+
<field>
29569+
<name>UTMI_TESTSTART</name>
29570+
<description>Setting this bit can enable 1</description>
29571+
<bitOffset>0</bitOffset>
29572+
<bitWidth>1</bitWidth>
29573+
<access>read-write</access>
29574+
</field>
29575+
</fields>
29576+
</register>
29577+
<register>
29578+
<name>USB1_LOOPBACK_SET</name>
29579+
<description>USB Loopback Test Register</description>
29580+
<addressOffset>0x1E4</addressOffset>
29581+
<size>32</size>
29582+
<access>read-write</access>
29583+
<resetValue>0</resetValue>
29584+
<resetMask>0xFFFFFFFF</resetMask>
29585+
<fields>
29586+
<field>
29587+
<name>UTMI_TESTSTART</name>
29588+
<description>Setting this bit can enable 1</description>
29589+
<bitOffset>0</bitOffset>
29590+
<bitWidth>1</bitWidth>
29591+
<access>read-write</access>
29592+
</field>
29593+
</fields>
29594+
</register>
29595+
<register>
29596+
<name>USB1_LOOPBACK_CLR</name>
29597+
<description>USB Loopback Test Register</description>
29598+
<addressOffset>0x1E8</addressOffset>
29599+
<size>32</size>
29600+
<access>read-write</access>
29601+
<resetValue>0</resetValue>
29602+
<resetMask>0xFFFFFFFF</resetMask>
29603+
<fields>
29604+
<field>
29605+
<name>UTMI_TESTSTART</name>
29606+
<description>Setting this bit can enable 1</description>
29607+
<bitOffset>0</bitOffset>
29608+
<bitWidth>1</bitWidth>
29609+
<access>read-write</access>
29610+
</field>
29611+
</fields>
29612+
</register>
29613+
<register>
29614+
<name>USB1_LOOPBACK_TOG</name>
29615+
<description>USB Loopback Test Register</description>
29616+
<addressOffset>0x1EC</addressOffset>
29617+
<size>32</size>
29618+
<access>read-write</access>
29619+
<resetValue>0</resetValue>
29620+
<resetMask>0xFFFFFFFF</resetMask>
29621+
<fields>
29622+
<field>
29623+
<name>UTMI_TESTSTART</name>
29624+
<description>Setting this bit can enable 1</description>
29625+
<bitOffset>0</bitOffset>
29626+
<bitWidth>1</bitWidth>
29627+
<access>read-write</access>
29628+
</field>
29629+
</fields>
29630+
</register>
2955929631
<register>
2956029632
<name>USB1_MISC</name>
2956129633
<description>USB Misc Register</description>
@@ -30382,6 +30454,78 @@ SPDX-License-Identifier: BSD-3-Clause
3038230454
</field>
3038330455
</fields>
3038430456
</register>
30457+
<register>
30458+
<name>USB2_LOOPBACK</name>
30459+
<description>USB Loopback Test Register</description>
30460+
<addressOffset>0x240</addressOffset>
30461+
<size>32</size>
30462+
<access>read-write</access>
30463+
<resetValue>0</resetValue>
30464+
<resetMask>0xFFFFFFFF</resetMask>
30465+
<fields>
30466+
<field>
30467+
<name>UTMI_TESTSTART</name>
30468+
<description>Setting this bit can enable 1</description>
30469+
<bitOffset>0</bitOffset>
30470+
<bitWidth>1</bitWidth>
30471+
<access>read-write</access>
30472+
</field>
30473+
</fields>
30474+
</register>
30475+
<register>
30476+
<name>USB2_LOOPBACK_SET</name>
30477+
<description>USB Loopback Test Register</description>
30478+
<addressOffset>0x244</addressOffset>
30479+
<size>32</size>
30480+
<access>read-write</access>
30481+
<resetValue>0</resetValue>
30482+
<resetMask>0xFFFFFFFF</resetMask>
30483+
<fields>
30484+
<field>
30485+
<name>UTMI_TESTSTART</name>
30486+
<description>Setting this bit can enable 1</description>
30487+
<bitOffset>0</bitOffset>
30488+
<bitWidth>1</bitWidth>
30489+
<access>read-write</access>
30490+
</field>
30491+
</fields>
30492+
</register>
30493+
<register>
30494+
<name>USB2_LOOPBACK_CLR</name>
30495+
<description>USB Loopback Test Register</description>
30496+
<addressOffset>0x248</addressOffset>
30497+
<size>32</size>
30498+
<access>read-write</access>
30499+
<resetValue>0</resetValue>
30500+
<resetMask>0xFFFFFFFF</resetMask>
30501+
<fields>
30502+
<field>
30503+
<name>UTMI_TESTSTART</name>
30504+
<description>Setting this bit can enable 1</description>
30505+
<bitOffset>0</bitOffset>
30506+
<bitWidth>1</bitWidth>
30507+
<access>read-write</access>
30508+
</field>
30509+
</fields>
30510+
</register>
30511+
<register>
30512+
<name>USB2_LOOPBACK_TOG</name>
30513+
<description>USB Loopback Test Register</description>
30514+
<addressOffset>0x24C</addressOffset>
30515+
<size>32</size>
30516+
<access>read-write</access>
30517+
<resetValue>0</resetValue>
30518+
<resetMask>0xFFFFFFFF</resetMask>
30519+
<fields>
30520+
<field>
30521+
<name>UTMI_TESTSTART</name>
30522+
<description>Setting this bit can enable 1</description>
30523+
<bitOffset>0</bitOffset>
30524+
<bitWidth>1</bitWidth>
30525+
<access>read-write</access>
30526+
</field>
30527+
</fields>
30528+
</register>
3038530529
<register>
3038630530
<name>USB2_MISC</name>
3038730531
<description>USB Misc Register</description>

‎sdk/devices/MIMXRT1052/MIMXRT1052_features.h‎

Lines changed: 73 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
/*
22
** ###################################################################
33
** Version: rev. 1.1, 2018-11-16
4-
** Build: b190319
4+
** Build: b200211
55
**
66
** Abstract:
77
** Chip specific module features.
88
**
99
** Copyright 2016 Freescale Semiconductor, Inc.
10-
** Copyright 2016-2019 NXP
10+
** Copyright 2016-2020 NXP
1111
** All rights reserved.
1212
**
1313
** SPDX-License-Identifier: BSD-3-Clause
@@ -127,6 +127,8 @@
127127
#define FSL_FEATURE_SOC_USBNC_COUNT (2)
128128
/* @brief USBPHY availability on the SoC. */
129129
#define FSL_FEATURE_SOC_USBPHY_COUNT (2)
130+
/* @brief USB_ANALOG availability on the SoC. */
131+
#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1)
130132
/* @brief USDHC availability on the SoC. */
131133
#define FSL_FEATURE_SOC_USDHC_COUNT (2)
132134
/* @brief WDOG availability on the SoC. */
@@ -151,6 +153,8 @@
151153

152154
/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
153155
#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
156+
/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
157+
#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (0)
154158

155159
/* AOI module features */
156160

@@ -195,6 +199,13 @@
195199
#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (0)
196200
/* @brief Has extra MB interrupt or common one. */
197201
#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1)
202+
/* @brief Has memory error control (register MECR). */
203+
#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0)
204+
205+
/* CCM module features */
206+
207+
/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
208+
#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (1)
198209

199210
/* CMP module features */
200211

@@ -211,6 +222,23 @@
211222
/* @brief Has DAC Test function in CMP (register DACTEST). */
212223
#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
213224

225+
/* DCDC module features */
226+
227+
/* @brief Has CTRL register (register CTRL0/1). */
228+
#define FSL_FEATURE_DCDC_HAS_CTRL_REG (0)
229+
/* @brief DCDC VDD output count. */
230+
#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1)
231+
/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */
232+
#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0)
233+
/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */
234+
#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0)
235+
/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */
236+
#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0)
237+
/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */
238+
#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0)
239+
/* @brief Has register bit field REG3[REG_FBK_SEL]). */
240+
#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0)
241+
214242
/* EDMA module features */
215243

216244
/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
@@ -255,6 +283,18 @@
255283
#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1)
256284
/* @brief Has Additional 1588 Timer Channel Interrupt. */
257285
#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
286+
/* @brief Support Interrupt Coalesce for each instance */
287+
#define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (1)
288+
/* @brief Queue Size for each instance. */
289+
#define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1)
290+
/* @brief Has AVB Support for each instance. */
291+
#define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0)
292+
/* @brief Has Timer Pulse Width control for each instance. */
293+
#define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (1)
294+
/* @brief Has Extend MDIO Support for each instance. */
295+
#define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1)
296+
/* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */
297+
#define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (0)
258298

259299
/* EWM module features */
260300

@@ -294,13 +334,19 @@
294334
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
295335
/* @brief Total Bank numbers */
296336
#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16)
337+
/* @brief Has FLEXRAM_MAGIC_ADDR. */
338+
#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (0)
297339

298340
/* FLEXSPI module features */
299341

300342
/* @brief FlexSPI AHB buffer count */
301343
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
302344
/* @brief FlexSPI has no data learn. */
303345
#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
346+
/* @brief There is AHBBUSERROREN bit in INTEN register. */
347+
#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0)
348+
/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
349+
#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
304350

305351
/* GPC module features */
306352

@@ -431,7 +477,12 @@
431477

432478
/* OCOTP module features */
433479

434-
/* No feature definitions */
480+
/* @brief Has timing control, (register TIMING). */
481+
#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1)
482+
/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
483+
#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0)
484+
/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
485+
#define FSL_FEATURE_OCOTP_HAS_STATUS (0)
435486

436487
/* PIT module features */
437488

@@ -453,24 +504,12 @@
453504

454505
/* PWM module features */
455506

456-
/* @brief Number of each EflexPWM module channels (outputs). */
457-
#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
458-
/* @brief Number of EflexPWM module A channels (outputs). */
459-
#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
460-
/* @brief Number of EflexPWM module B channels (outputs). */
461-
#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
462-
/* @brief Number of EflexPWM module X channels (outputs). */
463-
#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
464-
/* @brief Number of each EflexPWM module compare channels interrupts. */
465-
#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
466-
/* @brief Number of each EflexPWM module reload channels interrupts. */
467-
#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
468-
/* @brief Number of each EflexPWM module capture channels interrupts. */
469-
#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
470-
/* @brief Number of each EflexPWM module reload error channels interrupts. */
471-
#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
472-
/* @brief Number of each EflexPWM module fault channels interrupts. */
473-
#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
507+
/* @brief If EflexPWM has module A channels (outputs). */
508+
#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
509+
/* @brief If EflexPWM has module B channels (outputs). */
510+
#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
511+
/* @brief If EflexPWM has module X channels (outputs). */
512+
#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
474513
/* @brief Number of submodules in each EflexPWM module. */
475514
#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
476515

@@ -578,6 +617,8 @@
578617
#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0)
579618
/* @brief There is WDOG3_RST_B bit in SRSR register. */
580619
#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1)
620+
/* @brief There is JTAG_SW_RST bit in SRSR register. */
621+
#define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1)
581622
/* @brief There is SW bit in SRSR register. */
582623
#define FSL_FEATURE_SRC_HAS_SRSR_SW (0)
583624
/* @brief There is IPP_USER_RESET_B bit in SRSR register. */
@@ -616,6 +657,13 @@
616657
/* @brief Number of endpoints supported */
617658
#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
618659

660+
/* USBPHY module features */
661+
662+
/* @brief USBPHY contain DCD analog module */
663+
#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
664+
/* @brief USBPHY has register TRIM_OVERRIDE_EN */
665+
#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0)
666+
619667
/* USDHC module features */
620668

621669
/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */
@@ -626,6 +674,10 @@
626674
#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1)
627675
/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */
628676
#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1)
677+
/* @brief USDHC has reset control */
678+
#define FSL_FEATURE_USDHC_HAS_RESET (0)
679+
/* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */
680+
#define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (0)
629681

630682
/* XBARA module features */
631683

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