nxp_driver: Switch to v2.10.

Author: robert-hh

sdk/devices/MIMXRT1011/MIMXRT1011.h

@@ -11,13 +11,13 @@
 **
 **     Reference manual:    IMXRT1010RM Rev.0, 09/2019
 **     Version:             rev. 1.1, 2019-08-06
-**     Build:               b190916
+**     Build:               b201019
 **
 **     Abstract:
 **         CMSIS Peripheral Access Layer for MIMXRT1011
 **
 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -5671,6 +5671,160 @@ typedef struct {
  */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
 
 
+/* ----------------------------------------------------------------------------
+   -- CM7_MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer
+ * @{
+ */
+
+/** CM7_MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[16];
+  __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
+} CM7_MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM7_MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks
+ * @{
+ */
+
+/*! @name ISCR - Interrupt Status and Control Register */
+/*! @{ */
+#define CM7_MCM_ISCR_WABS_MASK                   (0x20U)
+#define CM7_MCM_ISCR_WABS_SHIFT                  (5U)
+/*! WABS - Write Abort on Slave
+ *  0b0..No abort
+ *  0b1..Abort
+ */
+#define CM7_MCM_ISCR_WABS(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
+#define CM7_MCM_ISCR_WABSO_MASK                  (0x40U)
+#define CM7_MCM_ISCR_WABSO_SHIFT                 (6U)
+/*! WABSO - Write Abort on Slave Overrun
+ *  0b0..No write abort overrun
+ *  0b1..Write abort overrun occurred
+ */
+#define CM7_MCM_ISCR_WABSO(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
+#define CM7_MCM_ISCR_FIOC_MASK                   (0x100U)
+#define CM7_MCM_ISCR_FIOC_SHIFT                  (8U)
+/*! FIOC - FPU Invalid Operation interrupt Status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FIOC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
+#define CM7_MCM_ISCR_FDZC_MASK                   (0x200U)
+#define CM7_MCM_ISCR_FDZC_SHIFT                  (9U)
+/*! FDZC - FPU Divide-by-Zero Interrupt Status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FDZC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
+#define CM7_MCM_ISCR_FOFC_MASK                   (0x400U)
+#define CM7_MCM_ISCR_FOFC_SHIFT                  (10U)
+/*! FOFC - FPU Overflow interrupt status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FOFC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
+#define CM7_MCM_ISCR_FUFC_MASK                   (0x800U)
+#define CM7_MCM_ISCR_FUFC_SHIFT                  (11U)
+/*! FUFC - FPU Underflow Interrupt Status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FUFC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
+#define CM7_MCM_ISCR_FIXC_MASK                   (0x1000U)
+#define CM7_MCM_ISCR_FIXC_SHIFT                  (12U)
+/*! FIXC - FPU Inexact Interrupt Status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FIXC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
+#define CM7_MCM_ISCR_FIDC_MASK                   (0x8000U)
+#define CM7_MCM_ISCR_FIDC_SHIFT                  (15U)
+/*! FIDC - FPU Input Denormal Interrupt Status
+ *  0b0..No interrupt
+ *  0b1..Interrupt occured
+ */
+#define CM7_MCM_ISCR_FIDC(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
+#define CM7_MCM_ISCR_WABE_MASK                   (0x200000U)
+#define CM7_MCM_ISCR_WABE_SHIFT                  (21U)
+/*! WABE - TCM Write Abort Interrupt enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_WABE(x)                     (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
+#define CM7_MCM_ISCR_FIOCE_MASK                  (0x1000000U)
+#define CM7_MCM_ISCR_FIOCE_SHIFT                 (24U)
+/*! FIOCE - FPU Invalid Operation Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FIOCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
+#define CM7_MCM_ISCR_FDZCE_MASK                  (0x2000000U)
+#define CM7_MCM_ISCR_FDZCE_SHIFT                 (25U)
+/*! FDZCE - FPU Divide-by-Zero Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FDZCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
+#define CM7_MCM_ISCR_FOFCE_MASK                  (0x4000000U)
+#define CM7_MCM_ISCR_FOFCE_SHIFT                 (26U)
+/*! FOFCE - FPU Overflow Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FOFCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
+#define CM7_MCM_ISCR_FUFCE_MASK                  (0x8000000U)
+#define CM7_MCM_ISCR_FUFCE_SHIFT                 (27U)
+/*! FUFCE - FPU Underflow Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FUFCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
+#define CM7_MCM_ISCR_FIXCE_MASK                  (0x10000000U)
+#define CM7_MCM_ISCR_FIXCE_SHIFT                 (28U)
+/*! FIXCE - FPU Inexact Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FIXCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
+#define CM7_MCM_ISCR_FIDCE_MASK                  (0x80000000U)
+#define CM7_MCM_ISCR_FIDCE_SHIFT                 (31U)
+/*! FIDCE - FPU Input Denormal Interrupt Enable
+ *  0b0..Disable interrupt
+ *  0b1..Enable interrupt
+ */
+#define CM7_MCM_ISCR_FIDCE(x)                    (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM7_MCM_Register_Masks */
+
+
+/* CM7_MCM - Peripheral instance base addresses */
+/** Peripheral CM7_MCM base address */
+#define CM7_MCM_BASE                             (0xE0080000u)
+/** Peripheral CM7_MCM base pointer */
+#define CM7_MCM                                  ((CM7_MCM_Type *)CM7_MCM_BASE)
+/** Array initializer of CM7_MCM peripheral base addresses */
+#define CM7_MCM_BASE_ADDRS                       { CM7_MCM_BASE }
+/** Array initializer of CM7_MCM peripheral base pointers */
+#define CM7_MCM_BASE_PTRS                        { CM7_MCM }
+
+/*!
+ * @}
+ */ /* end of group CM7_MCM_Peripheral_Access_Layer */
+
+
 /* ----------------------------------------------------------------------------
    -- CSU Peripheral Access Layer
    ---------------------------------------------------------------------------- */
@@ -8212,14 +8366,14 @@ typedef struct {
       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
     };
-    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
     union {                                          /* offset: 0x1016, array step: 0x20 */
       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
     };
-    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
     union {                                          /* offset: 0x101E, array step: 0x20 */
       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */

sdk/devices/MIMXRT1011/MIMXRT1011_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.0, 2019-08-01
-**     Build:               b200311
+**     Build:               b210329
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2020 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -129,6 +129,10 @@
 #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
 /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
 #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1)
+/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */
+#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (0)
+/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */
+#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (0)
 
 /* AOI module features */
 
@@ -177,17 +181,21 @@
 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
 /* @brief If 16 bytes transfer supported. */
 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0)
+/* @brief If 32 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1)
 
 /* DMAMUX module features */
 
 /* @brief Number of DMA channels (related to number of register CHCFGn). */
 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
 /* @brief Total number of DMA channels on all modules. */
-#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16)
+#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16)
 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */
 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1)
+/* @brief Register CHCFGn width. */
+#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32)
 
 /* EWM module features */
 
@@ -229,6 +237,8 @@
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4)
 /* @brief Has FLEXRAM_MAGIC_ADDR. */
 #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1)
+/* @brief If FLEXRAM has ECC function. */
+#define FSL_FEATURE_FLEXRAM_HAS_ECC (0)
 
 /* FLEXSPI module features */
 
@@ -315,10 +325,6 @@
 #define FSL_FEATURE_LPUART_IS_SCI (1)
 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4)
-/* @brief Maximal data width without parity bit. */
-#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
-/* @brief Maximal data width with parity bit. */
-#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
 /* @brief Supports two match addresses to filter incoming frames. */
 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
@@ -365,8 +371,6 @@
 #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1)
 /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
 #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0)
-/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
-#define FSL_FEATURE_OCOTP_HAS_STATUS (0)
 
 /* OTFAD module features */
 
@@ -394,14 +398,20 @@
 
 /* PWM module features */
 
-/* @brief If EflexPWM has module A channels (outputs). */
+/* @brief If (e)FlexPWM has module A channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELA (1)
-/* @brief If EflexPWM has module B channels (outputs). */
+/* @brief If (e)FlexPWM has module B channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELB (1)
-/* @brief If EflexPWM has module X channels (outputs). */
+/* @brief If (e)FlexPWM has module X channels (outputs). */
 #define FSL_FEATURE_PWM_HAS_CHANNELX (1)
-/* @brief Number of submodules in each EflexPWM module. */
+/* @brief If (e)FlexPWM has fractional feature. */
+#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1)
+/* @brief If (e)FlexPWM has mux trigger source select bit field. */
+#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
+/* @brief Number of submodules in each (e)FlexPWM module. */
 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
+/* @brief Number of fault channel in each (e)FlexPWM module. */
+#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
 
 /* RTWDOG module features */
 
@@ -451,6 +461,12 @@
 
 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */
 #define FSL_FEATURE_SNVS_HAS_SRTC (1)
+/* @brief Has Passive Tamper Filter (regitser LPTGFCR). */
+#define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0)
+/* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */
+#define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0)
+/* @brief Number of TAMPER. */
+#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (1)
 
 /* SRC module features */
 
@@ -534,6 +550,8 @@
 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
 /* @brief USBPHY has register TRIM_OVERRIDE_EN */
 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0)
+/* @brief USBPHY is 28FDSOI */
+#define FSL_FEATURE_USBPHY_28FDSOI (0)
 
 /* XBARA module features */
 

sdk/devices/MIMXRT1011/cmsis_drivers/driver_cmsis_lpi2c_MIMXRT1011.cmake

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpi2c component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpi2c_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpi2c_edma_MIMXRT1011)
+
+include(driver_lpi2c_MIMXRT1011)
+
+include(CMSIS_Driver_Include_I2C_MIMXRT1011)
+

sdk/devices/MIMXRT1011/cmsis_drivers/driver_cmsis_lpspi_MIMXRT1011.cmake

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpspi component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpspi_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpspi_edma_MIMXRT1011)
+
+include(driver_lpspi_MIMXRT1011)
+
+include(CMSIS_Driver_Include_SPI_MIMXRT1011)
+

sdk/devices/MIMXRT1011/cmsis_drivers/driver_cmsis_lpuart_MIMXRT1011.cmake

@@ -0,0 +1,19 @@
+include_guard(GLOBAL)
+message("driver_cmsis_lpuart component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_lpuart_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_lpuart_edma_MIMXRT1011)
+
+include(driver_lpuart_MIMXRT1011)
+
+include(CMSIS_Driver_Include_USART_MIMXRT1011)
+