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1 parent f64d8d7 commit fe7c4dfCopy full SHA for fe7c4df
1 file changed
nmigen_stdio/serial.py
@@ -81,6 +81,7 @@ def elaborate(self, platform):
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with m.State("IDLE"):
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with m.If(~self.i):
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m.d.sync += [
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+ shreg.eq(Repl(0, len(shreg))),
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bits_left.eq(len(shreg) - 1),
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timer.eq(self.divisor >> 1)
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]
@@ -119,7 +120,7 @@ def elaborate(self, platform):
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# (useful for divisor == 0)
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- shreg.eq(Cat(shreg[1:], self.i)),
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+ shreg.eq(Cat(Repl(0, len(shreg)-1), self.i)),
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bits_left.eq(len(shreg) - 2),
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timer.eq(self.divisor)
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