Fix test expectations and code formatting

- Fix LLVM code style: use trailing parameter alignment for
  getMatchingSuperReg calls instead of assignment-aligned continuation
- Update CHECK-FP16 expectations for atomic_load_half/bfloat: GlobalISel
  allocates FPR32 (s0) for GPR->FPR copies even with FullFP16, then
  narrows to h0 via kill annotation. The FullFP16 optimization only
  applies to FPR->GPR (store) direction where the value arrives in h0.
- Add kill annotations to CHECK-NOFP16 load tests to match actual output

Co-Authored-By: Claude <noreply@anthropic.com>

Author: IanButterworth

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -5858,8 +5858,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       BuildMI(MBB, I, DL, get(AArch64::FMOVWHr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      MCRegister DestRegS =
-          RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass);
+      MCRegister DestRegS = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
+                                                   &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestRegS)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -5871,8 +5871,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       BuildMI(MBB, I, DL, get(AArch64::FMOVHWr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      MCRegister SrcRegS =
-          RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass);
+      MCRegister SrcRegS = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
+                                                  &AArch64::FPR32RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
           .addReg(SrcRegS, RegState::Undef)
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
@@ -5887,8 +5887,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       BuildMI(MBB, I, DL, get(AArch64::FMOVXHr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      MCRegister DestRegD =
-          RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR64RegClass);
+      MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
+                                                   &AArch64::FPR64RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestRegD)
           .addReg(SrcReg, getKillRegState(KillSrc));
     }
@@ -5900,8 +5900,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       BuildMI(MBB, I, DL, get(AArch64::FMOVHXr), DestReg)
           .addReg(SrcReg, getKillRegState(KillSrc));
     } else {
-      MCRegister SrcRegD =
-          RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR64RegClass);
+      MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
+                                                  &AArch64::FPR64RegClass);
       BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
           .addReg(SrcRegD, RegState::Undef)
           .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-store-fp16.ll

@@ -27,12 +27,14 @@ define half @atomic_load_half(ptr %addr) {
 ; CHECK-NOFP16:       ; %bb.0:
 ; CHECK-NOFP16-NEXT:    ldarh w8, [x0]
 ; CHECK-NOFP16-NEXT:    fmov s0, w8
+; CHECK-NOFP16-NEXT:    ; kill: def $h0 killed $h0 killed $s0
 ; CHECK-NOFP16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: atomic_load_half:
 ; CHECK-FP16:       ; %bb.0:
 ; CHECK-FP16-NEXT:    ldarh w8, [x0]
-; CHECK-FP16-NEXT:    fmov h0, w8
+; CHECK-FP16-NEXT:    fmov s0, w8
+; CHECK-FP16-NEXT:    ; kill: def $h0 killed $h0 killed $s0
 ; CHECK-FP16-NEXT:    ret
   %ival = load atomic i16, ptr %addr acquire, align 2
   %val = bitcast i16 %ival to half
@@ -61,12 +63,14 @@ define bfloat @atomic_load_bfloat(ptr %addr) {
 ; CHECK-NOFP16:       ; %bb.0:
 ; CHECK-NOFP16-NEXT:    ldarh w8, [x0]
 ; CHECK-NOFP16-NEXT:    fmov s0, w8
+; CHECK-NOFP16-NEXT:    ; kill: def $h0 killed $h0 killed $s0
 ; CHECK-NOFP16-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: atomic_load_bfloat:
 ; CHECK-FP16:       ; %bb.0:
 ; CHECK-FP16-NEXT:    ldarh w8, [x0]
-; CHECK-FP16-NEXT:    fmov h0, w8
+; CHECK-FP16-NEXT:    fmov s0, w8
+; CHECK-FP16-NEXT:    ; kill: def $h0 killed $h0 killed $s0
 ; CHECK-FP16-NEXT:    ret
   %ival = load atomic i16, ptr %addr acquire, align 2
   %val = bitcast i16 %ival to bfloat