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[RISCV] Add OperandType for XSfmm TWiden. (#171572)
Use the same twiden format for PseudoSF_VSETTM and PseudoSF_VSETTK as other XSfmm pseudos. Though I don't think we use the operand from these instructions.
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5 files changed

+60
-46
lines changed

5 files changed

+60
-46
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,9 @@ enum OperandType : unsigned {
443443
OPERAND_VEC_RM,
444444
// Vtype operand for XSfmm extension.
445445
OPERAND_XSFMM_VTYPE,
446-
OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_VTYPE,
446+
// XSfmm twiden operand.
447+
OPERAND_XSFMM_TWIDEN,
448+
OPERAND_LAST_RISCV_IMM = OPERAND_XSFMM_TWIDEN,
447449

448450
OPERAND_UIMM20_LUI,
449451
OPERAND_UIMM20_AUIPC,

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1991,7 +1991,7 @@ bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
19911991
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
19921992
.addReg(Op.getReg())
19931993
.addImm(Log2_32(CurrInfo.getSEW()))
1994-
.addImm(Log2_32(CurrInfo.getTWiden()) + 1);
1994+
.addImm(CurrInfo.getTWiden());
19951995

19961996
Changed = true;
19971997
Register Reg = Op.getReg();

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3045,6 +3045,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
30453045
case RISCVOp::OPERAND_XSFMM_VTYPE:
30463046
Ok = RISCVVType::isValidXSfmmVType(Imm);
30473047
break;
3048+
case RISCVOp::OPERAND_XSFMM_TWIDEN:
3049+
Ok = Imm == 1 || Imm == 2 || Imm == 4;
3050+
break;
30483051
}
30493052
if (!Ok) {
30503053
ErrInfo = "Invalid immediate";
@@ -3775,6 +3778,11 @@ std::string RISCVInstrInfo::createMIROperandComment(
37753778
RISCVVType::printXSfmmVType(Imm, OS);
37763779
break;
37773780
}
3781+
case RISCVOp::OPERAND_XSFMM_TWIDEN: {
3782+
unsigned Imm = Op.getImm();
3783+
OS << "w" << Imm;
3784+
break;
3785+
}
37783786
case RISCVOp::OPERAND_SEW:
37793787
case RISCVOp::OPERAND_SEW_MASK: {
37803788
unsigned Log2SEW = Op.getImm();

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSfmm.td‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,10 @@ def XSfmmVTypeOp : RISCVOp {
3030
}];
3131
}
3232

33+
def twiden : RISCVOp {
34+
let OperandType = "OPERAND_XSFMM_TWIDEN";
35+
}
36+
3337
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
3438
class SFInstSetSingle<dag outs, dag ins, bits<5> rs2, string opcodestr,
3539
string argstr>
@@ -279,7 +283,7 @@ let Uses = [FRM], mayRaiseFPException = true in {
279283

280284
class VPseudoSF_VTileLoad
281285
: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn, sew:$sew,
282-
ixlenimm:$twiden)> {
286+
twiden:$twiden)> {
283287
let mayLoad = 1;
284288
let mayStore = 0;
285289
let HasVLOp = 1; // Tn
@@ -290,7 +294,7 @@ class VPseudoSF_VTileLoad
290294

291295
class VPseudoSF_VTileStore
292296
: RISCVVPseudo<(outs), (ins GPR:$rs2, GPR:$rs1, GPRNoX0:$atn, sew:$sew,
293-
ixlenimm:$twiden)> {
297+
twiden:$twiden)> {
294298
let mayLoad = 0;
295299
let mayStore = 1;
296300
let HasVLOp = 1; // Tn
@@ -301,7 +305,7 @@ class VPseudoSF_VTileStore
301305

302306
class VPseudoSF_VTileMove_V_T
303307
: RISCVVPseudo<(outs VRM8:$vd), (ins GPR:$rs1, GPRNoX0:$atn, sew:$sew,
304-
ixlenimm:$twiden)> {
308+
twiden:$twiden)> {
305309
let mayLoad = 0;
306310
let mayStore = 0;
307311
let HasVLOp = 1; // Tn
@@ -312,7 +316,7 @@ class VPseudoSF_VTileMove_V_T
312316

313317
class VPseudoSF_VTileMove_T_V
314318
: RISCVVPseudo<(outs), (ins GPR:$rs1, VRM8:$vs2, GPRNoX0:$atn, sew:$sew,
315-
ixlenimm:$twiden)> {
319+
twiden:$twiden)> {
316320
let mayLoad = 0;
317321
let mayStore = 0;
318322
let HasVLOp = 1; // Tn
@@ -325,7 +329,7 @@ class VPseudoSF_MatMul<RegisterClass mtd_class>
325329
: RISCVVPseudo<(outs),
326330
(ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, GPRNoX0:$atm,
327331
GPRNoX0:$atn, GPRNoX0:$atk, sew:$sew,
328-
ixlenimm:$twiden)> {
332+
twiden:$twiden)> {
329333
let mayLoad = 0;
330334
let mayStore = 0;
331335
let HasTmOp = 1;
@@ -340,7 +344,7 @@ class VPseudoSF_MatMul_FRM<RegisterClass mtd_class>
340344
: RISCVVPseudo<(outs),
341345
(ins mtd_class:$rd, VRM8:$vs2, VRM8:$vs1, ixlenimm:$frm,
342346
GPRNoX0:$atm, GPRNoX0:$atn, GPRNoX0:$atk, sew:$sew,
343-
ixlenimm:$twiden), []> {
347+
twiden:$twiden), []> {
344348
let mayLoad = 0;
345349
let mayStore = 0;
346350
let HasTmOp = 1;
@@ -376,12 +380,12 @@ let Defs = [VL, VTYPE] in {
376380
let Defs = [VTYPE], Uses = [VTYPE], HasTWidenOp = 1, HasSEWOp = 1 in {
377381
def PseudoSF_VSETTM
378382
: Pseudo<(outs GPR:$rd),
379-
(ins GPR:$rs1, sew:$sew, ixlenimm:$twiden), []>,
383+
(ins GPR:$rs1, sew:$sew, twiden:$twiden), []>,
380384
PseudoInstExpansion<(SF_VSETTM GPR:$rd, GPR:$rs1)>,
381385
Sched<[WriteVSETVLI, ReadVSETVLI]>;
382386
def PseudoSF_VSETTK
383387
: Pseudo<(outs GPR:$rd),
384-
(ins GPR:$rs1, sew:$sew, ixlenimm:$twiden), []>,
388+
(ins GPR:$rs1, sew:$sew, twiden:$twiden), []>,
385389
PseudoInstExpansion<(SF_VSETTK GPR:$rd, GPR:$rs1)>,
386390
Sched<[WriteVSETVLI, ReadVSETVLI]>;
387391
}
@@ -415,7 +419,7 @@ let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
415419
def PseudoSF_VTZERO_T
416420
: RISCVVPseudo<(outs),
417421
(ins TR:$rd, GPRNoX0:$atm, GPRNoX0:$atn, sew:$sew,
418-
ixlenimm:$twiden)>;
422+
twiden:$twiden)>;
419423
def PseudoSF_VTDISCARD : RISCVVPseudo<(outs), (ins), []>;
420424
}
421425

‎llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir‎

Lines changed: 35 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -122,12 +122,12 @@ body: |
122122
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
123123
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
124124
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
125-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
126-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
127-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
128-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
129-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
130-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
125+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
126+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
127+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
128+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
129+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
130+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
131131
; CHECK-NEXT: PseudoRET
132132
%4:gprnox0 = COPY $x12
133133
%3:gprnox0 = COPY $x11
@@ -169,13 +169,13 @@ body: |
169169
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
170170
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
171171
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
172-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
173-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
174-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
172+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
173+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
174+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
175175
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544 /* e16, w4 */, implicit-def $vl, implicit-def $vtype
176-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 3, implicit-def $vtype, implicit $vtype
177-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 3, implicit-def $vtype, implicit $vtype
178-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 4, implicit $frm, implicit $vl, implicit $vtype
176+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
177+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
178+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 4 /* w4 */, implicit $frm, implicit $vl, implicit $vtype
179179
; CHECK-NEXT: PseudoRET
180180
%4:gprnox0 = COPY $x12
181181
%3:gprnox0 = COPY $x11
@@ -217,17 +217,17 @@ body: |
217217
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
218218
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
219219
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
220-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
221-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
222-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
220+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
221+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
222+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
223223
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1288 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
224-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
225-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
226-
; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
224+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
225+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
226+
; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
227227
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
228-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
229-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
230-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
228+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
229+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
230+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
231231
; CHECK-NEXT: PseudoRET
232232
%4:gprnox0 = COPY $x12
233233
%3:gprnox0 = COPY $x11
@@ -268,11 +268,11 @@ body: |
268268
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8
269269
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
270270
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype
271-
; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1, implicit $vl, implicit $vtype
271+
; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype
272272
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
273273
; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
274274
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
275-
; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1, implicit $vl, implicit $vtype
275+
; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
276276
; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype
277277
; CHECK-NEXT: PseudoRET implicit $v8m8
278278
%2:gpr = COPY $x11
@@ -316,11 +316,11 @@ body: |
316316
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
317317
; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
318318
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype
319-
; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1, implicit $vl, implicit $vtype
319+
; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype
320320
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
321321
; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
322322
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
323-
; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1, implicit $vl, implicit $vtype
323+
; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
324324
; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype
325325
; CHECK-NEXT: PseudoRET implicit $v8m8
326326
%2:gpr = COPY $x11
@@ -365,11 +365,11 @@ body: |
365365
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x12
366366
; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gprnox0 = COPY $x13
367367
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
368-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
369-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4 /* e16 */, 2, implicit-def $vtype, implicit $vtype
370-
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2, implicit $frm, implicit $vl, implicit $vtype
368+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
369+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
370+
; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
371371
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
372-
; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4 /* e16 */, 1, implicit $vl, implicit $vtype
372+
; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
373373
; CHECK-NEXT: PseudoRET
374374
%0:vrm8 = COPY $v8m8
375375
%1:gprnox0 = COPY $x10
@@ -399,9 +399,9 @@ body: |
399399
; CHECK-NEXT: {{ $}}
400400
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
401401
; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
402-
; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1, implicit-def $vtype, implicit $vtype, implicit $vtype
402+
; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
403403
; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_1:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype
404-
; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1, implicit-def $vtype, implicit $vtype, implicit $vtype
404+
; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
405405
; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]
406406
; CHECK-NEXT: PseudoRET implicit $x10
407407
%0:gprnox0 = COPY $x10
@@ -430,7 +430,7 @@ body: |
430430
; CHECK-NEXT: {{ $}}
431431
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
432432
; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
433-
; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1, implicit-def $vtype, implicit $vtype, implicit $vtype
433+
; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
434434
; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]
435435
; CHECK-NEXT: PseudoRET implicit $x10
436436
%0:gprnox0 = COPY $x10
@@ -483,7 +483,7 @@ body: |
483483
; CHECK-NEXT: {{ $}}
484484
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
485485
; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
486-
; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1, implicit-def $vtype, implicit $vtype, implicit $vtype
486+
; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
487487
; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTK]]
488488
; CHECK-NEXT: PseudoRET implicit $x10
489489
%0:gprnox0 = COPY $x10
@@ -513,8 +513,8 @@ body: |
513513
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
514514
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11
515515
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1536 /* e8, w4 */, implicit-def $vl, implicit-def $vtype
516-
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3 /* e8 */, 3, implicit-def $vtype, implicit $vtype
517-
; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3 /* e8 */, 4, implicit $vl, implicit $vtype
516+
; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3 /* e8 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
517+
; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3 /* e8 */, 4 /* w4 */, implicit $vl, implicit $vtype
518518
; CHECK-NEXT: PseudoRET
519519
%0:gprnox0 = COPY $x10
520520
%1:gprnox0 = COPY $x11

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