Skip to content

Commit c3a0849

Browse files
authored
[CIR] Add support for the ArrayTypeTraitExpr (#171710)
Add support for the ArrayTypeTraitExpr
1 parent 4ea8157 commit c3a0849

File tree

2 files changed

+25
-3
lines changed

2 files changed

+25
-3
lines changed

clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -855,9 +855,9 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
855855
return builder.getBool(e->isSatisfied(), cgf.getLoc(e->getExprLoc()));
856856
}
857857
mlir::Value VisitArrayTypeTraitExpr(const ArrayTypeTraitExpr *e) {
858-
cgf.cgm.errorNYI(e->getSourceRange(),
859-
"ScalarExprEmitter: array type trait");
860-
return {};
858+
mlir::Type type = cgf.convertType(e->getType());
859+
mlir::Location loc = cgf.getLoc(e->getExprLoc());
860+
return builder.getConstInt(loc, type, e->getValue());
861861
}
862862
mlir::Value VisitExpressionTraitExpr(const ExpressionTraitExpr *e) {
863863
return builder.getBool(e->getValue(), cgf.getLoc(e->getExprLoc()));

clang/test/CIR/CodeGen/cxx-traits.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,3 +57,25 @@ void type_trait_expr() {
5757
// OGCG: store i8 0, ptr %[[B_ADDR]], align 1
5858
// OGCG: store i8 0, ptr %[[C_ADDR]], align 1
5959
// OGCG: store i8 0, ptr %[[D_ADDR]], align 1
60+
61+
void array_type_trait_expr() {
62+
unsigned long a = __array_rank(int[10][20]);
63+
unsigned long b = __array_extent(int[10][20], 1);
64+
}
65+
66+
// CIR: %[[A_ADDR:.*]] = cir.alloca !u64i, !cir.ptr<!u64i>, ["a", init]
67+
// CIR: %[[B_ADDR:.*]] = cir.alloca !u64i, !cir.ptr<!u64i>, ["b", init]
68+
// CIR: %[[CONST_2:.*]] = cir.const #cir.int<2> : !u64i
69+
// CIR: cir.store {{.*}} %[[CONST_2]], %[[A_ADDR]] : !u64i, !cir.ptr<!u64i>
70+
// CIR: %[[CONST_20:.*]] = cir.const #cir.int<20> : !u64i
71+
// CIR: cir.store {{.*}} %[[CONST_20]], %[[B_ADDR]] : !u64i, !cir.ptr<!u64i>
72+
73+
// LLVM: %[[A_ADDR:.*]] = alloca i64, i64 1, align 8
74+
// LLVM: %[[B_ADDR:.*]] = alloca i64, i64 1, align 8
75+
// LLVM: store i64 2, ptr %[[A_ADDR]], align 8
76+
// LLVM: store i64 20, ptr %[[B_ADDR]], align 8
77+
78+
// OGCG: %[[A_ADDR:.*]] = alloca i64, align 8
79+
// OGCG: %[[B_ADDR:.*]] = alloca i64, align 8
80+
// OGCG: store i64 2, ptr %[[A_ADDR]], align 8
81+
// OGCG: store i64 20, ptr %[[B_ADDR]], align 8

0 commit comments

Comments
 (0)