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IanButterworthclaude
IanButterworth
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claude
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[AArch64][GlobalISel] Fix incorrect codegen for FPR16/FPR8 to GPR copies
Previously, copyPhysReg() was missing handlers for copies between FPR16/FPR8 and GPR32/GPR64 register classes. These cases fell through to the NZCV handler, which incorrectly generated 'mrs Rd, NZCV' instead of the proper FMOV instruction. This caused incorrect code generation for patterns like: %ival = bitcast half %val to i16 store atomic i16 %ival, ptr %addr release, align 2 Which generated 'mrs w8, NZCV' instead of 'fmov w8, h0'. The fix adds proper copy handlers: - FPR16 <-> GPR32: Use FMOVHWr/FMOVWHr with FullFP16, otherwise promote to FPR32 super-register and use FMOVSWr/FMOVWSr - FPR16 <-> GPR64: Use FMOVHXr/FMOVXHr with FullFP16, otherwise promote to FPR64 super-register and use FMOVDXr/FMOVXDr - FPR8 <-> GPR32: Promote to FPR32 and use FMOVSWr/FMOVWSr - FPR8 <-> GPR64: Promote to FPR64 and use FMOVDXr/FMOVXDr Fixes #171494 Co-authored-by: Claude <noreply@anthropic.com>
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5804,6 +5804,102 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
58045804
return;
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}
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5807+
// Copies between GPR32 and FPR16.
5808+
if (AArch64::FPR16RegClass.contains(DestReg) &&
5809+
AArch64::GPR32RegClass.contains(SrcReg)) {
5810+
if (Subtarget.hasFullFP16()) {
5811+
BuildMI(MBB, I, DL, get(AArch64::FMOVWHr), DestReg)
5812+
.addReg(SrcReg, getKillRegState(KillSrc));
5813+
} else {
5814+
MCRegister DestRegS =
5815+
RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass);
5816+
BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestRegS)
5817+
.addReg(SrcReg, getKillRegState(KillSrc));
5818+
}
5819+
return;
5820+
}
5821+
if (AArch64::GPR32RegClass.contains(DestReg) &&
5822+
AArch64::FPR16RegClass.contains(SrcReg)) {
5823+
if (Subtarget.hasFullFP16()) {
5824+
BuildMI(MBB, I, DL, get(AArch64::FMOVHWr), DestReg)
5825+
.addReg(SrcReg, getKillRegState(KillSrc));
5826+
} else {
5827+
MCRegister SrcRegS =
5828+
RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass);
5829+
BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
5830+
.addReg(SrcRegS, RegState::Undef)
5831+
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
5832+
}
5833+
return;
5834+
}
5835+
5836+
// Copies between GPR64 and FPR16.
5837+
if (AArch64::FPR16RegClass.contains(DestReg) &&
5838+
AArch64::GPR64RegClass.contains(SrcReg)) {
5839+
if (Subtarget.hasFullFP16()) {
5840+
BuildMI(MBB, I, DL, get(AArch64::FMOVXHr), DestReg)
5841+
.addReg(SrcReg, getKillRegState(KillSrc));
5842+
} else {
5843+
MCRegister DestRegD =
5844+
RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR64RegClass);
5845+
BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestRegD)
5846+
.addReg(SrcReg, getKillRegState(KillSrc));
5847+
}
5848+
return;
5849+
}
5850+
if (AArch64::GPR64RegClass.contains(DestReg) &&
5851+
AArch64::FPR16RegClass.contains(SrcReg)) {
5852+
if (Subtarget.hasFullFP16()) {
5853+
BuildMI(MBB, I, DL, get(AArch64::FMOVHXr), DestReg)
5854+
.addReg(SrcReg, getKillRegState(KillSrc));
5855+
} else {
5856+
MCRegister SrcRegD =
5857+
RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR64RegClass);
5858+
BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
5859+
.addReg(SrcRegD, RegState::Undef)
5860+
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
5861+
}
5862+
return;
5863+
}
5864+
5865+
// Copies between GPR32 and FPR8.
5866+
if (AArch64::FPR8RegClass.contains(DestReg) &&
5867+
AArch64::GPR32RegClass.contains(SrcReg)) {
5868+
MCRegister DestRegS =
5869+
RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR32RegClass);
5870+
BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestRegS)
5871+
.addReg(SrcReg, getKillRegState(KillSrc));
5872+
return;
5873+
}
5874+
if (AArch64::GPR32RegClass.contains(DestReg) &&
5875+
AArch64::FPR8RegClass.contains(SrcReg)) {
5876+
MCRegister SrcRegS =
5877+
RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR32RegClass);
5878+
BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
5879+
.addReg(SrcRegS, RegState::Undef)
5880+
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
5881+
return;
5882+
}
5883+
5884+
// Copies between GPR64 and FPR8.
5885+
if (AArch64::FPR8RegClass.contains(DestReg) &&
5886+
AArch64::GPR64RegClass.contains(SrcReg)) {
5887+
MCRegister DestRegD =
5888+
RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR64RegClass);
5889+
BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestRegD)
5890+
.addReg(SrcReg, getKillRegState(KillSrc));
5891+
return;
5892+
}
5893+
if (AArch64::GPR64RegClass.contains(DestReg) &&
5894+
AArch64::FPR8RegClass.contains(SrcReg)) {
5895+
MCRegister SrcRegD =
5896+
RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR64RegClass);
5897+
BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
5898+
.addReg(SrcRegD, RegState::Undef)
5899+
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
5900+
return;
5901+
}
5902+
58075903
if (DestReg == AArch64::NZCV) {
58085904
assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
58095905
BuildMI(MBB, I, DL, get(AArch64::MSR))

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-store-fp16.ll‎

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,109 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-NOFP16
3+
; RUN: llc < %s -mtriple=arm64-apple-ios -mattr=+fullfp16 -global-isel -global-isel-abort=1 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-FP16
4+
5+
; Test for https://github.com/llvm/llvm-project/issues/171494
6+
; Atomic store of bitcast half to i16 was generating incorrect code (mrs instead of fmov).
7+
8+
define void @atomic_store_half(ptr %addr, half %val) {
9+
; CHECK-NOFP16-LABEL: atomic_store_half:
10+
; CHECK-NOFP16: ; %bb.0:
11+
; CHECK-NOFP16-NEXT: fmov w8, s0
12+
; CHECK-NOFP16-NEXT: stlrh w8, [x0]
13+
; CHECK-NOFP16-NEXT: ret
14+
;
15+
; CHECK-FP16-LABEL: atomic_store_half:
16+
; CHECK-FP16: ; %bb.0:
17+
; CHECK-FP16-NEXT: fmov w8, h0
18+
; CHECK-FP16-NEXT: stlrh w8, [x0]
19+
; CHECK-FP16-NEXT: ret
20+
%ival = bitcast half %val to i16
21+
store atomic i16 %ival, ptr %addr release, align 2
22+
ret void
23+
}
24+
25+
define half @atomic_load_half(ptr %addr) {
26+
; CHECK-NOFP16-LABEL: atomic_load_half:
27+
; CHECK-NOFP16: ; %bb.0:
28+
; CHECK-NOFP16-NEXT: ldarh w8, [x0]
29+
; CHECK-NOFP16-NEXT: fmov s0, w8
30+
; CHECK-NOFP16-NEXT: ret
31+
;
32+
; CHECK-FP16-LABEL: atomic_load_half:
33+
; CHECK-FP16: ; %bb.0:
34+
; CHECK-FP16-NEXT: ldarh w8, [x0]
35+
; CHECK-FP16-NEXT: fmov h0, w8
36+
; CHECK-FP16-NEXT: ret
37+
%ival = load atomic i16, ptr %addr acquire, align 2
38+
%val = bitcast i16 %ival to half
39+
ret half %val
40+
}
41+
42+
define void @atomic_store_bfloat(ptr %addr, bfloat %val) {
43+
; CHECK-NOFP16-LABEL: atomic_store_bfloat:
44+
; CHECK-NOFP16: ; %bb.0:
45+
; CHECK-NOFP16-NEXT: fmov w8, s0
46+
; CHECK-NOFP16-NEXT: stlrh w8, [x0]
47+
; CHECK-NOFP16-NEXT: ret
48+
;
49+
; CHECK-FP16-LABEL: atomic_store_bfloat:
50+
; CHECK-FP16: ; %bb.0:
51+
; CHECK-FP16-NEXT: fmov w8, h0
52+
; CHECK-FP16-NEXT: stlrh w8, [x0]
53+
; CHECK-FP16-NEXT: ret
54+
%ival = bitcast bfloat %val to i16
55+
store atomic i16 %ival, ptr %addr release, align 2
56+
ret void
57+
}
58+
59+
define bfloat @atomic_load_bfloat(ptr %addr) {
60+
; CHECK-NOFP16-LABEL: atomic_load_bfloat:
61+
; CHECK-NOFP16: ; %bb.0:
62+
; CHECK-NOFP16-NEXT: ldarh w8, [x0]
63+
; CHECK-NOFP16-NEXT: fmov s0, w8
64+
; CHECK-NOFP16-NEXT: ret
65+
;
66+
; CHECK-FP16-LABEL: atomic_load_bfloat:
67+
; CHECK-FP16: ; %bb.0:
68+
; CHECK-FP16-NEXT: ldarh w8, [x0]
69+
; CHECK-FP16-NEXT: fmov h0, w8
70+
; CHECK-FP16-NEXT: ret
71+
%ival = load atomic i16, ptr %addr acquire, align 2
72+
%val = bitcast i16 %ival to bfloat
73+
ret bfloat %val
74+
}
75+
76+
; Test FPR8 to GPR32 copies (bitcast <1 x i8> to i8 for atomic store)
77+
define void @atomic_store_v1i8(ptr %addr, <1 x i8> %val) {
78+
; CHECK-NOFP16-LABEL: atomic_store_v1i8:
79+
; CHECK-NOFP16: ; %bb.0:
80+
; CHECK-NOFP16-NEXT: fmov w8, s0
81+
; CHECK-NOFP16-NEXT: stlrb w8, [x0]
82+
; CHECK-NOFP16-NEXT: ret
83+
;
84+
; CHECK-FP16-LABEL: atomic_store_v1i8:
85+
; CHECK-FP16: ; %bb.0:
86+
; CHECK-FP16-NEXT: fmov w8, s0
87+
; CHECK-FP16-NEXT: stlrb w8, [x0]
88+
; CHECK-FP16-NEXT: ret
89+
%ival = bitcast <1 x i8> %val to i8
90+
store atomic i8 %ival, ptr %addr release, align 1
91+
ret void
92+
}
93+
94+
define <1 x i8> @atomic_load_v1i8(ptr %addr) {
95+
; CHECK-NOFP16-LABEL: atomic_load_v1i8:
96+
; CHECK-NOFP16: ; %bb.0:
97+
; CHECK-NOFP16-NEXT: ldarb w8, [x0]
98+
; CHECK-NOFP16-NEXT: fmov s0, w8
99+
; CHECK-NOFP16-NEXT: ret
100+
;
101+
; CHECK-FP16-LABEL: atomic_load_v1i8:
102+
; CHECK-FP16: ; %bb.0:
103+
; CHECK-FP16-NEXT: ldarb w8, [x0]
104+
; CHECK-FP16-NEXT: fmov s0, w8
105+
; CHECK-FP16-NEXT: ret
106+
%ival = load atomic i8, ptr %addr acquire, align 1
107+
%val = bitcast i8 %ival to <1 x i8>
108+
ret <1 x i8> %val
109+
}

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