@@ -423,15 +423,15 @@ int dpll_pin_parent_device_parse(struct ynl_parse_arg *yarg,
423423 } else if (type == DPLL_A_PIN_DIRECTION) {
424424 if (ynl_attr_validate (yarg, attr))
425425 return YNL_PARSE_CB_ERROR;
426- dst->direction = (dpll_pin_direction)ynl_attr_get_u32 (attr);
426+ dst->direction = (enum dpll_pin_direction)ynl_attr_get_u32 (attr);
427427 } else if (type == DPLL_A_PIN_PRIO) {
428428 if (ynl_attr_validate (yarg, attr))
429429 return YNL_PARSE_CB_ERROR;
430430 dst->prio = (__u32)ynl_attr_get_u32 (attr);
431431 } else if (type == DPLL_A_PIN_STATE) {
432432 if (ynl_attr_validate (yarg, attr))
433433 return YNL_PARSE_CB_ERROR;
434- dst->state = (dpll_pin_state)ynl_attr_get_u32 (attr);
434+ dst->state = (enum dpll_pin_state)ynl_attr_get_u32 (attr);
435435 } else if (type == DPLL_A_PIN_PHASE_OFFSET) {
436436 if (ynl_attr_validate (yarg, attr))
437437 return YNL_PARSE_CB_ERROR;
@@ -473,7 +473,7 @@ int dpll_pin_parent_pin_parse(struct ynl_parse_arg *yarg,
473473 } else if (type == DPLL_A_PIN_STATE) {
474474 if (ynl_attr_validate (yarg, attr))
475475 return YNL_PARSE_CB_ERROR;
476- dst->state = (dpll_pin_state)ynl_attr_get_u32 (attr);
476+ dst->state = (enum dpll_pin_state)ynl_attr_get_u32 (attr);
477477 }
478478 }
479479
@@ -511,7 +511,7 @@ int dpll_reference_sync_parse(struct ynl_parse_arg *yarg,
511511 } else if (type == DPLL_A_PIN_STATE) {
512512 if (ynl_attr_validate (yarg, attr))
513513 return YNL_PARSE_CB_ERROR;
514- dst->state = (dpll_pin_state)ynl_attr_get_u32 (attr);
514+ dst->state = (enum dpll_pin_state)ynl_attr_get_u32 (attr);
515515 }
516516 }
517517
@@ -601,17 +601,17 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
601601 } else if (type == DPLL_A_MODE) {
602602 if (ynl_attr_validate (yarg, attr))
603603 return YNL_PARSE_CB_ERROR;
604- dst->mode = (dpll_mode)ynl_attr_get_u32 (attr);
604+ dst->mode = (enum dpll_mode)ynl_attr_get_u32 (attr);
605605 } else if (type == DPLL_A_MODE_SUPPORTED) {
606606 n_mode_supported++;
607607 } else if (type == DPLL_A_LOCK_STATUS) {
608608 if (ynl_attr_validate (yarg, attr))
609609 return YNL_PARSE_CB_ERROR;
610- dst->lock_status = (dpll_lock_status)ynl_attr_get_u32 (attr);
610+ dst->lock_status = (enum dpll_lock_status)ynl_attr_get_u32 (attr);
611611 } else if (type == DPLL_A_LOCK_STATUS_ERROR) {
612612 if (ynl_attr_validate (yarg, attr))
613613 return YNL_PARSE_CB_ERROR;
614- dst->lock_status_error = (dpll_lock_status_error)ynl_attr_get_u32 (attr);
614+ dst->lock_status_error = (enum dpll_lock_status_error)ynl_attr_get_u32 (attr);
615615 } else if (type == DPLL_A_TEMP) {
616616 if (ynl_attr_validate (yarg, attr))
617617 return YNL_PARSE_CB_ERROR;
@@ -623,11 +623,11 @@ int dpll_device_get_rsp_parse(const struct nlmsghdr *nlh,
623623 } else if (type == DPLL_A_TYPE) {
624624 if (ynl_attr_validate (yarg, attr))
625625 return YNL_PARSE_CB_ERROR;
626- dst->type = (dpll_type)ynl_attr_get_u32 (attr);
626+ dst->type = (enum dpll_type)ynl_attr_get_u32 (attr);
627627 } else if (type == DPLL_A_PHASE_OFFSET_MONITOR) {
628628 if (ynl_attr_validate (yarg, attr))
629629 return YNL_PARSE_CB_ERROR;
630- dst->phase_offset_monitor = (dpll_feature_state)ynl_attr_get_u32 (attr);
630+ dst->phase_offset_monitor = (enum dpll_feature_state)ynl_attr_get_u32 (attr);
631631 }
632632 }
633633
@@ -832,7 +832,7 @@ int dpll_pin_get_rsp_parse(const struct nlmsghdr *nlh,
832832 } else if (type == DPLL_A_PIN_TYPE) {
833833 if (ynl_attr_validate (yarg, attr))
834834 return YNL_PARSE_CB_ERROR;
835- dst->type = (dpll_pin_type)ynl_attr_get_u32 (attr);
835+ dst->type = (enum dpll_pin_type)ynl_attr_get_u32 (attr);
836836 } else if (type == DPLL_A_PIN_FREQUENCY) {
837837 if (ynl_attr_validate (yarg, attr))
838838 return YNL_PARSE_CB_ERROR;
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