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1 parent 49da113 commit 1820d36Copy full SHA for 1820d36
swift/ql/lib/codeql/swift/dataflow/Ssa.qll
@@ -184,9 +184,7 @@ module Ssa {
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*/
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cached
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predicate assigns(CfgNode value) {
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- exists(
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- AssignExpr a, SsaInput::BasicBlock bb, int i
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- |
+ exists(AssignExpr a, SsaInput::BasicBlock bb, int i |
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this.definesAt(_, bb, i) and
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a = bb.getNode(i).getNode().asAstNode() and
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value.getNode().asAstNode() = a.getSource()
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