modified: arc_design_contest/2019/HUST_electrical_load_identification/main.c

	modified:   arc_design_contest/2019/HUST_electrical_load_identification/makefile
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_coefficients.c
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_constants.h
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_model.c
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_model.h
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/oled_display.c
	modified:   arc_design_contest/2019/HUST_electrical_load_identification/process.c

Author: tsinghua96

arc_design_contest/2019/HUST_electrical_load_identification/main.c

@@ -60,26 +60,29 @@ int main(void)
     display_welcome(&u8g);
     board_delay_ms(2000, 1);
 
-	EMBARC_PRINTF("Load Identification\r\n");
+	EMBARC_PRINTF("*************Load Identification****************\r\n");
     /* configuring GPIO to handle the "data ready" interrupt */
     while (1) {
         board_delay_ms(1, 1);
-		EMBARC_PRINTF("Hello ARC\r\n");
+//		EMBARC_PRINTF("Hello ARC\r\n");
 		if(proc_flag == 0){
 			if(one_frame_finish_flag == 0){
 				ad7991_adc_read(ad7991_sensor, ad_data);   
 				input_buffer_push_data(ad_data);     
 			}
 			else{
 				my_result = Cnn_Net_Classify();
+			    u8g_InitComFn(&u8g, &u8g_dev_ssd1306_128x64_2x_i2c, U8G_COM_SSD_I2C);
+			    u8g_Begin(&u8g); /* reset display and put it into default state */
 				display_result(&u8g, my_result);
 				one_frame_finish_flag = 0;
+				EMBARC_PRINTF("Result:%d\r\n",my_result);
 				proc_flag = 1;
 			}
 		}
 		else{
 			proc_flag = 0;
-			board_delay_ms(100, 1);
+			board_delay_ms(500, 1);
 		}
     }
     return E_SYS;

arc_design_contest/2019/HUST_electrical_load_identification/makefile

@@ -17,7 +17,7 @@ OLEVEL = O0
 #
 # root dir of embARC
 #
-EMBARC_ROOT = ../../../..
+EMBARC_ROOT = ../../
 
 # use -Hpurge option to optimize the code size
 ifeq ($(TOOLCHAIN), gnu)

arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_coefficients.c

@@ -49,23 +49,16 @@ extern const w_type  _W  L1_conv_bias_buf[];
 extern const w_type  _W  L2_conv_wt_buf[];
 extern const w_type  _W  L2_conv_bias_buf[];
 
-extern const w_type  _W2  L3_conv_wt_buf[];
-extern const w_type  _W2  L3_conv_bias_buf[];
 
-extern const w_type  _W2  L4_fc_wt_buf[];
-extern const w_type  _W2  L4_fc_bias_buf[];
+extern const w_type  _W2  L3_fc_wt_buf[];
+extern const w_type  _W2  L3_fc_bias_buf[];
 
-#if defined(MODEL_BIG)
-extern const w_type  _W2  L5_fc_wt_buf[];
-extern const w_type  _W2  L5_fc_bias_buf[];
-#endif
 
 //======================================================
 //
 // Tensor's Integer bits per layer definitions
 //
 //======================================================
-#if !defined(MODEL_BIG) // Small Model
 #if (MODEL_BIT_DEPTH == MODEL_FX_16)
 
 #define CONV1_W_INT   (-1)
@@ -76,13 +69,10 @@ extern const w_type  _W2  L5_fc_bias_buf[];
 #define CONV2_B_INT   (-1)
 #define CONV2_OUT_INT (5)
 
-#define CONV3_W_INT   (-1)
-#define CONV3_B_INT   (-2)
-#define CONV3_OUT_INT (6)
 
-#define FC4_W_INT   (-1)
-#define FC4_B_INT   (-2)
-#define FC4_OUT_INT (5)
+#define FC3_W_INT   (-1)
+#define FC3_B_INT   (-2)
+#define FC3_OUT_INT (5)
 
 #else //(MODEL_BIT_DEPTH == MODEL_FX_8 or MODEL_FX_8W16D)
 
@@ -94,65 +84,13 @@ extern const w_type  _W2  L5_fc_bias_buf[];
 #define CONV2_B_INT   (-1)
 #define CONV2_OUT_INT (5)
 
-#define CONV3_W_INT   (-1)
-#define CONV3_B_INT   (-2)
-#define CONV3_OUT_INT (5)
 
-#define FC4_W_INT   (-1)
-#define FC4_B_INT   (-2)
-#define FC4_OUT_INT (5)
+#define FC3_W_INT   (-1)
+#define FC3_B_INT   (-2)
+#define FC3_OUT_INT (5)
 
 #endif
 
-#else // Big Model
-#if (MODEL_BIT_DEPTH == MODEL_FX_16)
-
-#define CONV1_W_INT   (0)
-#define CONV1_B_INT   (0)
-#define CONV1_OUT_INT (5)
-
-#define CONV2_W_INT   (-1)
-#define CONV2_B_INT   (-1)
-#define CONV2_OUT_INT (6)
-
-#define CONV3_W_INT   (-2)
-#define CONV3_B_INT   (-2)
-#define CONV3_OUT_INT (5)
-
-#define FC4_W_INT   (-1)
-#define FC4_B_INT   (-3)
-#define FC4_OUT_INT (3)
-
-#define FC5_W_INT   (0)
-#define FC5_B_INT   (-2)
-#define FC5_OUT_INT (5)
-
-
-#else //(MODEL_BIT_DEPTH == MODEL_FX_8 or MODEL_FX_8W16D)
-
-#define CONV1_W_INT   (0)
-#define CONV1_B_INT   (0)
-#define CONV1_OUT_INT (4)
-
-#define CONV2_W_INT   (-1)
-#define CONV2_B_INT   (-1)
-#define CONV2_OUT_INT (5)
-
-#define CONV3_W_INT   (-2)
-#define CONV3_B_INT   (-2)
-#define CONV3_OUT_INT (4)
-
-#define FC4_W_INT   (-2)
-#define FC4_B_INT   (-3)
-#define FC4_OUT_INT (3)
-
-#define FC5_W_INT   (0)
-#define FC5_B_INT   (-2)
-#define FC5_OUT_INT (5)
-
-#endif
-#endif
-
 //======================================================
 //
 // Shape and Fractional bits per layer definitions
@@ -161,15 +99,15 @@ extern const w_type  _W2  L5_fc_bias_buf[];
 
 // CONV1
 //================================================
-#define CONV1_W_SHAPE {32,3,5,5}
-#define CONV1_W_ELEMENTS (32*3*5*5)
+#define CONV1_W_SHAPE {4,1,5,5}
+#define CONV1_W_ELEMENTS (4*1*5*5)
 #define CONV1_W_RANK (4)
 
 #define CONV1_W_FRAQ   (FRQ_BITS(CONV1_W_INT, w_type))
 #define L1_WQ(val)   QMN(w_type, CONV1_W_FRAQ, val)
 
-#define CONV1_B_ELEMENTS (32)
-#define CONV1_B_SHAPE {32}
+#define CONV1_B_ELEMENTS (4)
+#define CONV1_B_SHAPE {4}
 #define CONV1_B_RANK (1)
 
 #define CONV1_B_FRAQ   (FRQ_BITS(CONV1_B_INT, w_type))
@@ -179,17 +117,10 @@ extern const w_type  _W2  L5_fc_bias_buf[];
 
 // CONV2
 //================================================
-#if defined(MODEL_BIG)
-#define CONV2_W_SHAPE {32,32,5,5}
-#define CONV2_W_ELEMENTS (32*32*5*5)
-#define CONV2_B_SHAPE {32}
-#define CONV2_B_ELEMENTS (32)
-#else // Small Model
-#define CONV2_W_SHAPE {16,32,5,5}
-#define CONV2_W_ELEMENTS (16*32*5*5)
-#define CONV2_B_SHAPE {16}
-#define CONV2_B_ELEMENTS (16)
-#endif
+#define CONV2_W_SHAPE {2,4,5,5}
+#define CONV2_W_ELEMENTS (2*4*5*5)
+#define CONV2_B_SHAPE {2}
+#define CONV2_B_ELEMENTS (2)
 
 #define CONV2_W_RANK (4)
 #define CONV2_B_RANK (1)
@@ -200,51 +131,21 @@ extern const w_type  _W2  L5_fc_bias_buf[];
 #define L2_BQ(val)   QMN(w_type, CONV2_B_FRAQ, val)
 #define CONV2_OUT_FRAQ (FRQ_BITS(CONV2_OUT_INT, d_type))
 
-// CONV3
-//================================================
-#if defined(MODEL_BIG)
-#define CONV3_W_SHAPE {64,32,5,5}
-#define CONV3_W_ELEMENTS (64*32*5*5)
-#define CONV3_B_SHAPE {64}
-#define CONV3_B_ELEMENTS (64)
-#else // Small Model
-#define CONV3_W_SHAPE {32,16,5,5}
-#define CONV3_W_ELEMENTS (32*16*5*5)
-#define CONV3_B_SHAPE {32}
-#define CONV3_B_ELEMENTS (32)
-#endif
-#define CONV3_W_RANK (4)
-#define CONV3_B_RANK (1)
-
-#define CONV3_W_FRAQ   (FRQ_BITS(CONV2_W_INT, w_type))
-#define L3_WQ(val)   QMN(w_type, CONV2_W_FRAQ, val)
-#define CONV3_B_FRAQ   (FRQ_BITS(CONV2_B_INT, w_type))
-#define L3_BQ(val)   QMN(w_type, CONV2_B_FRAQ, val)
-#define CONV3_OUT_FRAQ (FRQ_BITS(CONV2_OUT_INT, d_type))
 
-// FC4
+// FC3
 //================================================
-#if defined(MODEL_BIG)
-#define FC4_W_SHAPE {64,(64*16)}
-#define FC4_W_ELEMENTS (64*(64*16))
-#define FC4_B_SHAPE {64}
-#define FC4_B_ELEMENTS (64)
-#else // Small Model
-#define FC4_W_SHAPE {10,(32*16)}
-#define FC4_W_ELEMENTS (10*(32*16))
-#define FC4_B_SHAPE {10}
-#define FC4_B_ELEMENTS (10)
-#endif
-#define FC4_W_RANK (2)
-#define FC4_B_RANK (1)
-
-#define FC4_W_FRAQ   (FRQ_BITS(FC4_W_INT, w_type))
-#define L4_WQ(val)   QMN(w_type, FC4_W_FRAQ, val)
-#define FC4_B_FRAQ   (FRQ_BITS(FC4_B_INT, w_type))
-#define L4_BQ(val)   QMN(w_type, FC4_B_FRAQ, val)
-#define FC4_OUT_FRAQ (FRQ_BITS(FC4_OUT_INT, d_type))
-
-
+#define FC3_W_SHAPE {6,(7*7*4)}
+#define FC3_W_ELEMENTS (6*(7*7*4))
+#define FC3_B_SHAPE {6}
+#define FC3_B_ELEMENTS (6)
+#define FC3_W_RANK (2)
+#define FC3_B_RANK (1)
+
+#define FC3_W_FRAQ   (FRQ_BITS(FC3_W_INT, w_type))
+#define L3_WQ(val)   QMN(w_type, FC3_W_FRAQ, val)
+#define FC3_B_FRAQ   (FRQ_BITS(FC3_B_INT, w_type))
+#define L3_BQ(val)   QMN(w_type, FC3_B_FRAQ, val)
+#define FC3_OUT_FRAQ (FRQ_BITS(FC3_OUT_INT, d_type))
 
 
 

arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_constants.h

@@ -41,27 +41,27 @@
 
 // Intermediate data buffers (enough size for max intermediate results)
 //==============================
-#define IR_BUF_SZ_MOST (32*32*32) //32768
-#define IR_BUF_SZ_NEXT (32*16*16)
+#define IR_BUF_SZ_MOST (28*28*28) //32768
+#define IR_BUF_SZ_NEXT (28*14*14)
 static d_type  _Z    x_mem_buf[IR_BUF_SZ_MOST];
 static d_type  _Y    y_mem_buf[IR_BUF_SZ_NEXT];
 
 // Module Input/Output tensors and their's external interface
 //============================================================
 static mli_tensor input = {
 	.data = (void *)x_mem_buf,
-	.capacity = sizeof(d_type) * (28 * 28 * 1),
-	.shape = IN_POINTS,
+	.capacity = sizeof(d_type) * IN_POINTS,
+	.shape = {28, 28, 1},
 	.rank = 3,
 	.el_type = D_EL_TYPE,
 	.el_params.fx.frac_bits = 7,
 };
 
 static mli_tensor output = {
 	.data = (void *)y_mem_buf,
-	.capacity = sizeof(d_type) * (10),
+	.capacity = sizeof(d_type) * OUT_POINTS,
 	.shape = OUT_POINTS,
-	.rank = 1,
+	.rank = {6},
 	.el_type = D_EL_TYPE,
 	.el_params.fx.frac_bits = 0,
 };
@@ -142,45 +142,26 @@ static mli_tensor L2_conv_bias = {
 };
 
 
-// Conv 3 Layer related data
-//===================================
-static mli_tensor L3_conv_wt = {
-	.data = (void *)L3_conv_wt_buf,
-	.capacity = CONV3_W_ELEMENTS * sizeof(w_type),
-	.shape = CONV3_W_SHAPE,
-	.rank = CONV3_W_RANK,
-	.el_type = W_EL_TYPE,
-	.el_params.fx.frac_bits = CONV3_W_FRAQ,
-};
-
-static mli_tensor L3_conv_bias = {
-	.data = (void *)L3_conv_bias_buf,
-	.capacity = CONV3_B_ELEMENTS * sizeof(w_type),
-	.shape = CONV3_B_SHAPE,
-	.rank = CONV3_B_RANK,
-	.el_type = W_EL_TYPE,
-	.el_params.fx.frac_bits = CONV3_B_FRAQ,
-};
 
 
-// FC4 Layer related data
+// FC3 Layer related data
 //===================================
-static mli_tensor L4_fc_wt = {
-	.data = (void *)L4_fc_wt_buf,
-	.capacity = FC4_W_ELEMENTS * sizeof(w_type),
-	.shape = FC4_W_SHAPE,
-	.rank = FC4_W_RANK,
+static mli_tensor L3_fc_wt = {
+	.data = (void *)L3_fc_wt_buf,
+	.capacity = FC3_W_ELEMENTS * sizeof(w_type),
+	.shape = FC3_W_SHAPE,
+	.rank = FC3_W_RANK,
 	.el_type = W_EL_TYPE,
-	.el_params.fx.frac_bits = FC4_W_FRAQ,
+	.el_params.fx.frac_bits = FC3_W_FRAQ,
 };
 
-static mli_tensor L4_fc_bias = {
-	.data = (void *)L4_fc_bias_buf,
-	.capacity = FC4_B_ELEMENTS * sizeof(w_type),
-	.shape = FC4_B_SHAPE,
-	.rank = FC4_B_RANK,
+static mli_tensor L3_fc_bias = {
+	.data = (void *)L3_fc_bias_buf,
+	.capacity = FC3_B_ELEMENTS * sizeof(w_type),
+	.shape = FC3_B_SHAPE,
+	.rank = FC3_B_RANK,
 	.el_type = W_EL_TYPE,
-	.el_params.fx.frac_bits = FC4_B_FRAQ,
+	.el_params.fx.frac_bits = FC3_B_FRAQ,
 };
 
 
@@ -255,19 +236,12 @@ void load_identification_net(void) {
 	//=======================================
 	ir_tensor_X.el_params.fx.frac_bits = CONV2_OUT_FRAQ;
 	conv2d_chw(&ir_tensor_Y, &L2_conv_wt, &L2_conv_bias, &shared_conv_cfg, &ir_tensor_X);
-	avepool_chw(&ir_tensor_X, &shared_pool_cfg, &ir_tensor_Y);
+	maxpool_chw(&ir_tensor_X, &shared_pool_cfg, &ir_tensor_Y);
 
 	// LAYER 3
 	//=======================================
-	ir_tensor_X.el_params.fx.frac_bits = CONV3_OUT_FRAQ;
-	conv2d_chw(&ir_tensor_Y, &L3_conv_wt, &L3_conv_bias, &shared_conv_cfg, &ir_tensor_X);
-	avepool_chw(&ir_tensor_X, &shared_pool_cfg, &ir_tensor_Y);
-
-	// LAYER 4
-	//=======================================
-	ir_tensor_X.el_params.fx.frac_bits = FC4_OUT_FRAQ;
-	fully_connected(&ir_tensor_Y, &L4_fc_wt, &L4_fc_bias, &ir_tensor_X);
-
+	ir_tensor_X.el_params.fx.frac_bits = FC3_OUT_FRAQ;
+	fully_connected(&ir_tensor_Y, &L3_fc_wt, &L3_fc_bias, &ir_tensor_X);
 
 	softmax(&ir_tensor_X, &output);
 

arc_design_contest/2019/HUST_electrical_load_identification/model/load_identification_model.c

@@ -25,7 +25,7 @@
 extern mli_tensor * const load_identification_net_input;
 #define IN_POINTS (28 * 28 * 1)
 extern mli_tensor * const load_identification_net_output;
-#define OUT_POINTS (10)
+#define OUT_POINTS (6)
 
 extern void load_identification_net(void);