arc: Put DBNZ instruction to a separate class

DBNZ instruction decrements its source register operand, and if
the result is non-zero it branches to the location defined by a signed
half-word displacement operand.

DBNZ instruction is in BRANCH class as other branch instrucitons
like B, Bcc, etc. However, DBNZ is the only branch instruction
that stores a branch offset in the second operand. Thus it must
be placed in a distinct class and treated differently.

For example, current logic of arc_insn_get_branch_target in GDB
assumes that a branch offset is always stored in the first operand
for BRANCH class and it's wrong for DBNZ.

include/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* opcode/arc.h (enum insn_class_t): Add DBNZ class.

opcodes/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* arc-tbl.h (dbnz): Use "DBNZ" class.
	* arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.

gas/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".

Author: kolerov

gas/config/tc-arc.c

@@ -114,6 +114,7 @@ enum arc_rlx_types
 				  || (op)->insn_class == BBIT0		\
 				  || (op)->insn_class == BBIT1		\
 				  || (op)->insn_class == BI		\
+				  || (op)->insn_class == DBNZ		\
 				  || (op)->insn_class == EI		\
 				  || (op)->insn_class == ENTER		\
 				  || (op)->insn_class == JLI		\

include/opcode/arc.h

@@ -52,6 +52,7 @@ typedef enum
   BRANCH,
   BRCC,
   CONTROL,
+  DBNZ,
   DIVREM,
   DMA,
   DPI,

opcodes/arc-dis.c

@@ -979,6 +979,7 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
     case BI:
     case BIH:
     case BRCC:
+    case DBNZ:
     case EI:
     case JLI:
     case JUMP:

opcodes/arc-tbl.h

@@ -3656,7 +3656,7 @@
 { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
-{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DBNZ, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
 
 /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
 { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},