From dc561fd34f7a3e7ff9922f48ad19082f83211bb5 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 23 Oct 2024 11:39:11 +0100 Subject: [PATCH 1/8] meson: default to no targets unless a probe cross-file is given Previously when configuring the build for a probe manually, the default would be to enable all debug targets This could lead to user confusion as the build would fail due to lack of space for some probes, for this reason an edge case condition was added to override the defaults, the method employed does have a problems, it prevents enabling all targets explicitly for the affected probems, even if the user knows what they are doing, and increases the maintenance burden as a list of enabled targets needs to be maintained in multiple places This makes it so the default for manually configured builds (i.e. not using the pre-made cross-files) is to not enable *any* debug targets, they must be configured manually, this gives a clear warning if one would forget to do this, and removes the maintenance burden with duplicate lists --- meson_options.txt | 1 + src/target/meson.build | 22 ---------------------- 2 files changed, 1 insertion(+), 22 deletions(-) diff --git a/meson_options.txt b/meson_options.txt index 9129524f380..c439d385358 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -50,6 +50,7 @@ option( 'ti', 'xilinx' ], + value: [], description: 'Enabled debug targets' ) option( diff --git a/src/target/meson.build b/src/target/meson.build index f04bd7f1226..7f12113cbb4 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -95,28 +95,6 @@ if is_firmware_build 'ti': 'Texas Instruments parts', 'xilinx': 'Xilinx parts', } - - # Check to see if the set of enabled targets is all of them and the - # firmware is to be built for a STM32F1 based probe (requires a restriction) - if probe in ['bluepill', 'native', 'stlink', 'swlink'] and enabled_targets.length() == target_names.keys().length() - warning('Disabling some targets as your build will not fit the target probe otherwise') - enabled_targets = ['cortexm', 'lpc', 'nrf', 'nxp', 'renesas', 'rp', 'sam', 'stm', 'ti'] - elif probe in ['f072'] and enabled_targets.length() == target_names.keys().length() - warning('Disabling some targets as your build will not fit the target probe otherwise') - enabled_targets = [ - 'cortexm', - 'riscv32', - 'riscv64', - 'lpc', - 'nrf', - 'nxp', - 'renesas', - 'rp', - 'sam', - 'stm', - 'ti' - ] - endif endif # Conditional file compilation based on target selection From 4070da9352edf85243e597c5d2a726fb1d86a09d Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 23 Oct 2024 12:46:12 +0100 Subject: [PATCH 2/8] meson: integrate debug target descriptive name into the target declaration --- src/target/meson.build | 158 ++++++++++++++++++++++++++++++++--------- 1 file changed, 124 insertions(+), 34 deletions(-) diff --git a/src/target/meson.build b/src/target/meson.build index 7f12113cbb4..194e00ba0b3 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -68,39 +68,14 @@ if is_firmware_build See the 'targets' option for a list of available targets. ''', ) - - # Build a dictionary mapping all target short names to proper textual naming - target_names = { - 'cortexar': 'Cortex-A/R support', - 'cortexm': 'Cortex-M support', - 'riscv32': 'RISC-V 32-bit support', - 'riscv64': 'RISC-V 64-bit support', - 'at32f4': 'Arterytek parts', - 'apollo3': 'Ambiq Apollo3 parts', - 'ch32': 'WinChipHead CH32 ARM Cortex parts', - 'ch32v': 'WinChipHead CH32 RISC-V parts', - 'ch579': 'WinChipHead CH579 parts', - 'efm': 'Energy Micro parts', - 'gd32': 'GigaDevice parts', - 'hc32': 'HC32 parts', - 'lpc': 'LPC series parts', - 'mm32': 'MindMotion parts', - 'nrf': 'nRF series parts', - 'nxp': 'Kinetis series parts', - 'puya': 'Puya PY32 series parts', - 'renesas': 'Renesas parts', - 'rp': 'Raspberry Pi MCUs (RP2040, RP2350)', - 'sam': 'ATSAM series parts', - 'stm': 'STM32 (and clones) parts', - 'ti': 'Texas Instruments parts', - 'xilinx': 'Xilinx parts', - } endif # Conditional file compilation based on target selection # We declare a dependency for each target group with the source files required # these dependencies are then added to the BMD core, conditinal on the targets option # NOTE: sourceset module might be an alternative to this method (unexplored) +target_names = [] # List of all target names + target_arm_coresight = declare_dependency( sources: files('arm_coresight_cti.c'), ) @@ -113,18 +88,30 @@ target_cortexar = declare_dependency( sources: files('cortexar.c'), dependencies: target_cortex, compile_args: ['-DCONFIG_CORTEXAR=1'], + variables: { + 'description': 'Cortex-A/R support' + } ) +target_names += 'cortexar' target_cortexm = declare_dependency( sources: files('cortexm.c'), dependencies: target_cortex, compile_args: ['-DCONFIG_CORTEXM=1'], + variables: { + 'description': 'Cortex-M support' + } ) +target_names += 'cortexm' target_cortexa_armv8 = declare_dependency( sources: files('cortexa_armv8.c'), dependencies: [target_cortex, target_arm_coresight], + variables: { + 'description': 'Cortex-A armv8 support' + } ) +target_names += 'cortexa_armv8' riscv_jtag_dtm = declare_dependency( sources: files( @@ -144,24 +131,40 @@ target_riscv = declare_dependency( target_riscv32 = declare_dependency( sources: files('riscv32.c'), dependencies: target_riscv, + variables: { + 'description': 'RISC-V 32-bit support' + }, ) +target_names += 'riscv32' target_riscv64 = declare_dependency( sources: files('riscv64.c'), dependencies: target_riscv, + variables: { + 'description': 'RISC-V 64-bit support' + }, ) +target_names += 'riscv64' target_apollo3 = declare_dependency( sources: files('apollo3.c'), compile_args: ['-DCONFIG_APOLLO3=1'], dependencies: target_cortexm, + variables: { + 'description': 'Ambiq Apollo3 parts' + }, ) +target_names += 'apollo3' target_ch579 = declare_dependency( sources: files('ch579.c'), compile_args: ['-DCONFIG_CH579=1'], dependencies: target_cortexm, + variables: { + 'description': 'WinChipHead CH579' + }, ) +target_names += 'ch579' target_efm = declare_dependency( sources: files( @@ -169,13 +172,21 @@ target_efm = declare_dependency( ) + efm32_stub, compile_args: ['-DCONFIG_EFM32=1'], dependencies: target_cortexm, + variables: { + 'description': 'Energy Micro parts' + }, ) +target_names += 'efm' target_hc32 = declare_dependency( sources: files('hc32l110.c'), compile_args: ['-DCONFIG_HC32=1'], dependencies: target_cortexm, + variables: { + 'description': 'HC32 parts' + }, ) +target_names += 'hc32' target_lpc = declare_dependency( sources: files( @@ -190,7 +201,11 @@ target_lpc = declare_dependency( ), compile_args: ['-DCONFIG_LPC=1'], dependencies: target_cortexm, + variables: { + 'description': 'LPC series parts' + }, ) +target_names += 'lpc' target_nrf = declare_dependency( sources: files( @@ -200,7 +215,11 @@ target_nrf = declare_dependency( ), compile_args: ['-DCONFIG_NRF=1'], dependencies: target_cortexm, + variables: { + 'description': 'nRF series parts' + }, ) +target_names += 'nrf' target_nxp = declare_dependency( sources: files( @@ -211,13 +230,21 @@ target_nxp = declare_dependency( ), compile_args: ['-DCONFIG_NXP=1'], dependencies: target_cortexm, + variables: { + 'description': 'Kinetis series parts' + }, ) +target_names += 'nxp' target_puya = declare_dependency( sources: files('puya.c'), compile_args: ['-DCONFIG_PUYA=1'], dependencies: target_cortexm, + variables: { + 'description': 'Puya PY32 series parts' + }, ) +target_names += 'puya' target_renesas_ra = declare_dependency( sources: files('renesas_ra.c'), @@ -233,13 +260,20 @@ target_renesas_rz = declare_dependency( # If the Cortex-A/R target is not enabled, don't enable Renesas RZ part support if not is_firmware_build or enabled_targets.contains('cortexar') -target_renesas = [ +target_renesas_deps = [ target_renesas_ra, target_renesas_rz, ] else -target_renesas = target_renesas_ra +target_renesas_deps = target_renesas_ra endif +target_renesas = declare_dependency( + dependencies: target_renesas_deps, + variables: { + 'description': 'Renesas parts' + }, +) +target_names += 'renesas' target_rp = declare_dependency( sources: files( @@ -248,7 +282,11 @@ target_rp = declare_dependency( ) + rp2040_stub, compile_args: ['-DCONFIG_RP=1'], dependencies: target_cortexm, + variables: { + 'description': 'Raspberry Pi MCUs (RP2040, RP2350)' + }, ) +target_names += 'rp' target_sam = declare_dependency( sources: files( @@ -259,7 +297,11 @@ target_sam = declare_dependency( ), compile_args: ['-DCONFIG_SAM=1'], dependencies: target_cortexm, + variables: { + 'description': 'ATSAM series parts' + }, ) +target_names += 'sam' target_stm_common = declare_dependency( sources: files( @@ -278,14 +320,22 @@ target_stm32f1 = declare_dependency( 'stm32f1.c', ), dependencies: target_stm32f1_deps, + variables: { + 'description': 'STM32F1 parts' + }, ) +target_names += 'stm32f1' target_stm32f4 = declare_dependency( sources: files( 'stm32f4.c', ), dependencies: [target_cortexm, target_stm_common], + variables: { + 'description': 'STM32F4 parts' + }, ) +target_names += 'stm32f4' target_ch32 = declare_dependency( sources: files( @@ -293,14 +343,22 @@ target_ch32 = declare_dependency( ), compile_args: ['-DCONFIG_CH32=1'], dependencies: target_stm32f1, + variables: { + 'description': 'WinChipHead CH32 ARM Cortex parts' + }, ) +target_names += 'ch32' target_ch32v = declare_dependency( sources: files( 'ch32vx.c', ), dependencies: target_riscv32, + variables: { + 'description': 'WinChipHead CH32 RISC-V parts' + }, ) +target_names += 'ch32v' target_stm = declare_dependency( sources: files( @@ -314,25 +372,41 @@ target_stm = declare_dependency( ), compile_args: ['-DCONFIG_STM=1'], dependencies: [target_cortexm, target_stm_common, target_stm32f1, target_stm32f4], + variables: { + 'description': 'STM32 parts' + }, ) +target_names += 'stm' target_gd32 = declare_dependency( dependencies: [target_stm32f1, target_stm32f4], compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice parts' + }, ) +target_names += 'gd32' target_mm32 = declare_dependency( dependencies: target_stm32f1, compile_args: ['-DCONFIG_MM32=1'], + variables: { + 'description': 'MindMotion parts' + }, ) +target_names += 'mm32' target_at32f4 = declare_dependency( sources: files( 'at32f43x.c', ), compile_args: ['-DCONFIG_AT32=1'], - dependencies: [target_cortexm, target_stm_common] + dependencies: [target_cortexm, target_stm_common], + variables: { + 'description': 'Arterytek parts' + }, ) +target_names += 'at32f4' target_ti = declare_dependency( sources: files( @@ -343,7 +417,11 @@ target_ti = declare_dependency( ) + lmi_stub, compile_args: ['-DCONFIG_TI=1'], dependencies: target_cortexm, + variables: { + 'description': 'Texas Instruments parts' + }, ) +target_names += 'ti' target_xilinx = declare_dependency( sources: files( @@ -351,7 +429,11 @@ target_xilinx = declare_dependency( ), dependencies: target_cortexar, compile_args: ['-DCONFIG_XILINX=1'], + variables: { + 'description': 'Xilinx parts' + }, ) +target_names += 'xilinx' if is_firmware_build # Convert targets option list into a list of dependencies @@ -423,14 +505,22 @@ libbmd_targets = declare_dependency( if is_firmware_build # Build a dictionary of the targets that have been selected for the firmware build - target_states = {} - foreach target_id, target_name : target_names - target_states += {target_name: target_id in enabled_targets} + target_summary = {} + foreach target : target_names + # Get the target dependency object + target_dep = get_variable(f'target_@target@') + + # Get the target description, defaulting to the base target name if not set + target_description = target_dep.get_variable('description', default_value: target) + + # Add the target enabled status to the summary + target_enabled = target in enabled_targets + target_summary += {target_description: target_enabled} endforeach # Include the target enable list in the summary output summary( - target_states, + target_summary, bool_yn: true, section: 'Targets', ) From 91313c05e101534d20f28d9cb6b2703b370fb0f7 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Wed, 23 Oct 2024 12:47:26 +0100 Subject: [PATCH 3/8] meson: automatically build dependency list for libbmd This automatically adds all targets to the libbmd dependencies removing the need to manually update this list when new targets are added --- src/target/meson.build | 34 +++++----------------------------- 1 file changed, 5 insertions(+), 29 deletions(-) diff --git a/src/target/meson.build b/src/target/meson.build index 194e00ba0b3..3439eaecce9 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -466,35 +466,11 @@ if is_firmware_build ) endif -libbmd_target_deps = [ - # Enable all architectures for libbmd - target_cortexar, - target_cortexm, - target_cortexa_armv8, - target_riscv32, - target_riscv64, - # Enable all targets for libbmd - target_apollo3, - target_at32f4, - target_ch32, - target_ch32v, - target_ch579, - target_efm, - target_gd32, - target_hc32, - target_lpc, - target_mm32, - target_nrf, - target_nxp, - target_puya, - target_renesas_ra, - target_renesas_rz, - target_rp, - target_sam, - target_stm, - target_ti, - target_xilinx, -] +# Enable all architectures and targets for libbmd +libbmd_target_deps = [] +foreach target : target_names + libbmd_target_deps += get_variable(f'target_@target@') +endforeach # Define the libbmd target dependency libbmd_targets = declare_dependency( From a6ee532d31e67aab1d80d4caccd7fcee0adfa175 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Tue, 29 Oct 2024 12:01:37 +0000 Subject: [PATCH 4/8] meson: decouple enable_riscv_accel from the debug target configuration although it is tied to the debug target configuration being dependent on riscv_jtag_dtm, this option just sets a define and is better grouped with other similar configuration options --- src/meson.build | 7 +++++++ src/target/meson.build | 16 ---------------- 2 files changed, 7 insertions(+), 16 deletions(-) diff --git a/src/meson.build b/src/meson.build index bb71a4b7410..5afcba3d162 100644 --- a/src/meson.build +++ b/src/meson.build @@ -93,6 +93,12 @@ if advertise_noackmode libbmd_core_args += ['-DADVERTISE_NOACKMODE=1'] endif +# Check if we should enable the RISC-V Debug remote protocol acceleration and do so if required +enable_riscv_accel = get_option('enable_riscv_accel') +if enable_riscv_accel + bmd_core_args += ['-DCONFIG_RISCV_ACCEL=1'] +endif + # Get BMD targets dependency subdir('target') @@ -126,6 +132,7 @@ summary( 'RTT support': rtt_support, 'RVSWD support': rvswd_support, 'Advertise QStartNoAckMode': advertise_noackmode, + 'RISC-V acceleration': enable_riscv_accel, }, bool_yn: true, section: 'Black Magic Debug', diff --git a/src/target/meson.build b/src/target/meson.build index 3439eaecce9..91abe27136c 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -442,22 +442,6 @@ if is_firmware_build enabled_target_deps += get_variable(f'target_@target@') endforeach - # Check if we should enable the RISC-V Debug remote protocol acceleration and do so if required - enable_riscv_accel = get_option('enable_riscv_accel') - if enable_riscv_accel - enabled_target_deps += declare_dependency( - compile_args: ['-DCONFIG_RISCV_ACCEL=1'], - dependencies: riscv_jtag_dtm, - ) - endif - - summary( - 'RISC-V acceleration', - enable_riscv_accel, - bool_yn: true, - section: 'Remote Protocol', - ) - # BMD target dependency bmd_targets = declare_dependency( include_directories: target_common_includes, From edf05dc0f3fc9a4f6bacff93c6a683fb5e39d0a4 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Mon, 4 Nov 2024 10:48:18 +0000 Subject: [PATCH 5/8] meson: streamline target declaration store the dependency objects themselves instead of strings massage the target declarations to remove conditional targets based on which targets are enabled --- meson_options.txt | 5 ++ src/target/meson.build | 166 ++++++++++++++++++----------------------- 2 files changed, 79 insertions(+), 92 deletions(-) diff --git a/meson_options.txt b/meson_options.txt index c439d385358..9e848e0069e 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -37,15 +37,20 @@ option( 'ch579', 'efm', 'gd32', + 'gd32_rv', 'hc32', 'lpc', 'mm32', 'nrf', 'nxp', 'puya', + 'renesas_ra', + 'renesas_rz', 'renesas', 'rp', 'sam', + 'stm32f1', + 'stm32f4', 'stm', 'ti', 'xilinx' diff --git a/src/target/meson.build b/src/target/meson.build index 91abe27136c..3d3c5a1d720 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -58,60 +58,48 @@ if get_option('no_own_ll') ) endif -if is_firmware_build - enabled_targets = get_option('targets') - - # Check that at least one target is enabled - assert( - enabled_targets.length() > 0, - '''No debug targets enabled, please enable at least one target to build. - See the 'targets' option for a list of available targets. - ''', - ) -endif - # Conditional file compilation based on target selection # We declare a dependency for each target group with the source files required # these dependencies are then added to the BMD core, conditinal on the targets option # NOTE: sourceset module might be an alternative to this method (unexplored) -target_names = [] # List of all target names +all_targets = [] -target_arm_coresight = declare_dependency( +arm_coresight = declare_dependency( sources: files('arm_coresight_cti.c'), ) -target_cortex = declare_dependency( +cortex_common = declare_dependency( sources: files('cortex.c'), ) target_cortexar = declare_dependency( sources: files('cortexar.c'), - dependencies: target_cortex, + dependencies: cortex_common, compile_args: ['-DCONFIG_CORTEXAR=1'], variables: { 'description': 'Cortex-A/R support' } ) -target_names += 'cortexar' +all_targets += target_cortexar target_cortexm = declare_dependency( sources: files('cortexm.c'), - dependencies: target_cortex, + dependencies: cortex_common, compile_args: ['-DCONFIG_CORTEXM=1'], variables: { 'description': 'Cortex-M support' } ) -target_names += 'cortexm' +all_targets += target_cortexm target_cortexa_armv8 = declare_dependency( sources: files('cortexa_armv8.c'), - dependencies: [target_cortex, target_arm_coresight], + dependencies: [cortex_common, arm_coresight], variables: { 'description': 'Cortex-A armv8 support' } ) -target_names += 'cortexa_armv8' +all_targets += target_cortexa_armv8 riscv_jtag_dtm = declare_dependency( sources: files( @@ -119,7 +107,7 @@ riscv_jtag_dtm = declare_dependency( ), ) -target_riscv = declare_dependency( +riscv_common = declare_dependency( sources: files( 'riscv_debug.c', 'riscv_adi_dtm.c', @@ -130,21 +118,21 @@ target_riscv = declare_dependency( target_riscv32 = declare_dependency( sources: files('riscv32.c'), - dependencies: target_riscv, + dependencies: riscv_common, variables: { 'description': 'RISC-V 32-bit support' }, ) -target_names += 'riscv32' +all_targets += target_riscv32 target_riscv64 = declare_dependency( sources: files('riscv64.c'), - dependencies: target_riscv, + dependencies: riscv_common, variables: { 'description': 'RISC-V 64-bit support' }, ) -target_names += 'riscv64' +all_targets += target_riscv64 target_apollo3 = declare_dependency( sources: files('apollo3.c'), @@ -154,7 +142,7 @@ target_apollo3 = declare_dependency( 'description': 'Ambiq Apollo3 parts' }, ) -target_names += 'apollo3' +all_targets += target_apollo3 target_ch579 = declare_dependency( sources: files('ch579.c'), @@ -164,7 +152,7 @@ target_ch579 = declare_dependency( 'description': 'WinChipHead CH579' }, ) -target_names += 'ch579' +all_targets += target_ch579 target_efm = declare_dependency( sources: files( @@ -176,7 +164,7 @@ target_efm = declare_dependency( 'description': 'Energy Micro parts' }, ) -target_names += 'efm' +all_targets += target_efm target_hc32 = declare_dependency( sources: files('hc32l110.c'), @@ -186,7 +174,7 @@ target_hc32 = declare_dependency( 'description': 'HC32 parts' }, ) -target_names += 'hc32' +all_targets += target_hc32 target_lpc = declare_dependency( sources: files( @@ -205,7 +193,7 @@ target_lpc = declare_dependency( 'description': 'LPC series parts' }, ) -target_names += 'lpc' +all_targets += target_lpc target_nrf = declare_dependency( sources: files( @@ -219,7 +207,7 @@ target_nrf = declare_dependency( 'description': 'nRF series parts' }, ) -target_names += 'nrf' +all_targets += target_nrf target_nxp = declare_dependency( sources: files( @@ -234,7 +222,7 @@ target_nxp = declare_dependency( 'description': 'Kinetis series parts' }, ) -target_names += 'nxp' +all_targets += target_nxp target_puya = declare_dependency( sources: files('puya.c'), @@ -244,36 +232,29 @@ target_puya = declare_dependency( 'description': 'Puya PY32 series parts' }, ) -target_names += 'puya' +all_targets += target_puya target_renesas_ra = declare_dependency( sources: files('renesas_ra.c'), compile_args: ['-DCONFIG_RA=1'], dependencies: target_cortexm, + variables: { + 'description': 'Renesas RA parts' + }, ) +all_targets += target_renesas_ra target_renesas_rz = declare_dependency( sources: files('renesas_rz.c'), compile_args: ['-DCONFIG_RZ=1'], dependencies: target_cortexar, -) - -# If the Cortex-A/R target is not enabled, don't enable Renesas RZ part support -if not is_firmware_build or enabled_targets.contains('cortexar') -target_renesas_deps = [ - target_renesas_ra, - target_renesas_rz, -] -else -target_renesas_deps = target_renesas_ra -endif -target_renesas = declare_dependency( - dependencies: target_renesas_deps, variables: { - 'description': 'Renesas parts' + 'description': 'Renesas RZ parts' }, ) -target_names += 'renesas' +all_targets += target_renesas_rz + +target_renesas = [target_renesas_ra, target_renesas_rz] target_rp = declare_dependency( sources: files( @@ -286,7 +267,7 @@ target_rp = declare_dependency( 'description': 'Raspberry Pi MCUs (RP2040, RP2350)' }, ) -target_names += 'rp' +all_targets += target_rp target_sam = declare_dependency( sources: files( @@ -301,41 +282,35 @@ target_sam = declare_dependency( 'description': 'ATSAM series parts' }, ) -target_names += 'sam' +all_targets += target_sam -target_stm_common = declare_dependency( +stm_common = declare_dependency( sources: files( 'stm32_common.c', ) ) -target_stm32f1_deps = [target_cortexm, target_stm_common] -# If the 32-bit RISC-V target is not enabled, don't enable GD32VF103 support -if not is_firmware_build or enabled_targets.contains('riscv32') - target_stm32f1_deps += [target_riscv32] -endif - target_stm32f1 = declare_dependency( sources: files( 'stm32f1.c', ), - dependencies: target_stm32f1_deps, + dependencies: [target_cortexm, stm_common], variables: { 'description': 'STM32F1 parts' }, ) -target_names += 'stm32f1' +all_targets += target_stm32f1 target_stm32f4 = declare_dependency( sources: files( 'stm32f4.c', ), - dependencies: [target_cortexm, target_stm_common], + dependencies: [target_cortexm, stm_common], variables: { 'description': 'STM32F4 parts' }, ) -target_names += 'stm32f4' +all_targets += target_stm32f4 target_ch32 = declare_dependency( sources: files( @@ -347,7 +322,7 @@ target_ch32 = declare_dependency( 'description': 'WinChipHead CH32 ARM Cortex parts' }, ) -target_names += 'ch32' +all_targets += target_ch32 target_ch32v = declare_dependency( sources: files( @@ -358,7 +333,7 @@ target_ch32v = declare_dependency( 'description': 'WinChipHead CH32 RISC-V parts' }, ) -target_names += 'ch32v' +all_targets += target_ch32v target_stm = declare_dependency( sources: files( @@ -371,12 +346,12 @@ target_stm = declare_dependency( 'stm32wb0.c', ), compile_args: ['-DCONFIG_STM=1'], - dependencies: [target_cortexm, target_stm_common, target_stm32f1, target_stm32f4], + dependencies: [target_cortexm, stm_common, target_stm32f1, target_stm32f4], variables: { 'description': 'STM32 parts' }, ) -target_names += 'stm' +all_targets += target_stm target_gd32 = declare_dependency( dependencies: [target_stm32f1, target_stm32f4], @@ -385,7 +360,16 @@ target_gd32 = declare_dependency( 'description': 'GigaDevice parts' }, ) -target_names += 'gd32' +all_targets += target_gd32 + +target_gd32_rv = declare_dependency( + dependencies: [target_gd32, target_riscv32], + compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice Risc-V parts' + }, +) +all_targets += target_gd32_rv target_mm32 = declare_dependency( dependencies: target_stm32f1, @@ -394,19 +378,19 @@ target_mm32 = declare_dependency( 'description': 'MindMotion parts' }, ) -target_names += 'mm32' +all_targets += target_mm32 target_at32f4 = declare_dependency( sources: files( 'at32f43x.c', ), compile_args: ['-DCONFIG_AT32=1'], - dependencies: [target_cortexm, target_stm_common], + dependencies: [target_cortexm, stm_common], variables: { 'description': 'Arterytek parts' }, ) -target_names += 'at32f4' +all_targets += target_at32f4 target_ti = declare_dependency( sources: files( @@ -421,7 +405,7 @@ target_ti = declare_dependency( 'description': 'Texas Instruments parts' }, ) -target_names += 'ti' +all_targets += target_ti target_xilinx = declare_dependency( sources: files( @@ -433,49 +417,47 @@ target_xilinx = declare_dependency( 'description': 'Xilinx parts' }, ) -target_names += 'xilinx' +all_targets += target_xilinx if is_firmware_build # Convert targets option list into a list of dependencies - enabled_target_deps = [] - foreach target : enabled_targets - enabled_target_deps += get_variable(f'target_@target@') + enabled_bmd_targets = [] + foreach target : get_option('targets') + enabled_bmd_targets += get_variable(f'target_@target@') endforeach + # Check that at least one target is enabled + assert( + enabled_bmd_targets.length() > 0, + '''No debug targets enabled, please enable at least one target to build. + See the 'targets' option for a list of available targets. + ''', + ) + # BMD target dependency bmd_targets = declare_dependency( include_directories: target_common_includes, sources: target_common_sources, - dependencies: enabled_target_deps, + dependencies: enabled_bmd_targets, ) endif -# Enable all architectures and targets for libbmd -libbmd_target_deps = [] -foreach target : target_names - libbmd_target_deps += get_variable(f'target_@target@') -endforeach - -# Define the libbmd target dependency +# Define the libbmd target dependency, enable all architectures and targets libbmd_targets = declare_dependency( include_directories: target_common_includes, sources: target_common_sources, - dependencies: libbmd_target_deps, + dependencies: all_targets, ) if is_firmware_build # Build a dictionary of the targets that have been selected for the firmware build target_summary = {} - foreach target : target_names - # Get the target dependency object - target_dep = get_variable(f'target_@target@') - - # Get the target description, defaulting to the base target name if not set - target_description = target_dep.get_variable('description', default_value: target) + foreach target : all_targets + # Get the target description + target_description = target.get_variable('description') # Add the target enabled status to the summary - target_enabled = target in enabled_targets - target_summary += {target_description: target_enabled} + target_summary += {target_description: target in enabled_bmd_targets} endforeach # Include the target enable list in the summary output From 1b43b67452b444bfeeef4e0766ff14a17d9fd1cc Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Tue, 5 Nov 2024 15:48:49 +0000 Subject: [PATCH 6/8] cross-file: update default target list after a small rewrite the name of the target options changed slightly, meaning more targets were enabled by default than before this commit adjusts this to retain the previous behavior --- cross-file/bluepill.ini | 2 +- cross-file/f072.ini | 2 +- cross-file/native.ini | 2 +- cross-file/swlink.ini | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cross-file/bluepill.ini b/cross-file/bluepill.ini index 50028721002..11937ff2664 100644 --- a/cross-file/bluepill.ini +++ b/cross-file/bluepill.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'bluepill' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = true diff --git a/cross-file/f072.ini b/cross-file/f072.ini index 2382d205205..6429b018307 100644 --- a/cross-file/f072.ini +++ b/cross-file/f072.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'f072' -targets = 'cortexm,riscv32,riscv64,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,riscv32,riscv64,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = false diff --git a/cross-file/native.ini b/cross-file/native.ini index 2aaae354ad4..c92ee9c66a7 100644 --- a/cross-file/native.ini +++ b/cross-file/native.ini @@ -22,6 +22,6 @@ endian = 'little' [project options] probe = 'native' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = true diff --git a/cross-file/swlink.ini b/cross-file/swlink.ini index 3a744b7675f..099c761dcff 100644 --- a/cross-file/swlink.ini +++ b/cross-file/swlink.ini @@ -19,6 +19,6 @@ endian = 'little' [project options] probe = 'swlink' -targets = 'cortexm,lpc,nrf,nxp,renesas,rp,sam,stm,ti' +targets = 'cortexm,lpc,nrf,nxp,renesas_ra,rp,sam,stm,ti' rtt_support = false bmd_bootloader = false From 70d00eb93574dddfe31cd4ea62891cd775f17698 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Mon, 18 Aug 2025 12:57:44 +0100 Subject: [PATCH 7/8] meson: move flashstubs inclusion for organization reasons --- src/target/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/meson.build b/src/target/meson.build index 3d3c5a1d720..d2372434109 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -29,10 +29,10 @@ # OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -target_common_includes = include_directories('.') - subdir('flashstub') +target_common_includes = include_directories('.') + target_common_sources = files( 'adi.c', 'adiv5.c', From 1fd83e7a5cf58ee613c76719e3bc2478ec3cad20 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Mon, 18 Aug 2025 13:56:37 +0100 Subject: [PATCH 8/8] meson: further streamline target declaration Use a dictionary in place of named variables and the get variable method --- src/target/meson.build | 673 +++++++++++++++++++++-------------------- 1 file changed, 345 insertions(+), 328 deletions(-) diff --git a/src/target/meson.build b/src/target/meson.build index d2372434109..3048fb1a483 100644 --- a/src/target/meson.build +++ b/src/target/meson.build @@ -62,7 +62,6 @@ endif # We declare a dependency for each target group with the source files required # these dependencies are then added to the BMD core, conditinal on the targets option # NOTE: sourceset module might be an alternative to this method (unexplored) -all_targets = [] arm_coresight = declare_dependency( sources: files('arm_coresight_cti.c'), @@ -72,34 +71,31 @@ cortex_common = declare_dependency( sources: files('cortex.c'), ) -target_cortexar = declare_dependency( - sources: files('cortexar.c'), - dependencies: cortex_common, - compile_args: ['-DCONFIG_CORTEXAR=1'], - variables: { - 'description': 'Cortex-A/R support' - } -) -all_targets += target_cortexar - -target_cortexm = declare_dependency( - sources: files('cortexm.c'), - dependencies: cortex_common, - compile_args: ['-DCONFIG_CORTEXM=1'], - variables: { - 'description': 'Cortex-M support' - } -) -all_targets += target_cortexm - -target_cortexa_armv8 = declare_dependency( - sources: files('cortexa_armv8.c'), - dependencies: [cortex_common, arm_coresight], - variables: { - 'description': 'Cortex-A armv8 support' - } -) -all_targets += target_cortexa_armv8 +targets = { + 'cortexar': declare_dependency( + sources: files('cortexar.c'), + dependencies: cortex_common, + compile_args: ['-DCONFIG_CORTEXAR=1'], + variables: { + 'description': 'Cortex-A/R support' + } + ), + 'cortexm': declare_dependency( + sources: files('cortexm.c'), + dependencies: cortex_common, + compile_args: ['-DCONFIG_CORTEXM=1'], + variables: { + 'description': 'Cortex-M support' + } + ), + 'cortexa_armv8': declare_dependency( + sources: files('cortexa_armv8.c'), + dependencies: [cortex_common, arm_coresight], + variables: { + 'description': 'Cortex-A armv8 support' + } + ) +} riscv_jtag_dtm = declare_dependency( sources: files( @@ -116,173 +112,190 @@ riscv_common = declare_dependency( dependencies: riscv_jtag_dtm, ) -target_riscv32 = declare_dependency( - sources: files('riscv32.c'), - dependencies: riscv_common, - variables: { - 'description': 'RISC-V 32-bit support' - }, -) -all_targets += target_riscv32 - -target_riscv64 = declare_dependency( - sources: files('riscv64.c'), - dependencies: riscv_common, - variables: { - 'description': 'RISC-V 64-bit support' - }, -) -all_targets += target_riscv64 - -target_apollo3 = declare_dependency( - sources: files('apollo3.c'), - compile_args: ['-DCONFIG_APOLLO3=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Ambiq Apollo3 parts' - }, -) -all_targets += target_apollo3 - -target_ch579 = declare_dependency( - sources: files('ch579.c'), - compile_args: ['-DCONFIG_CH579=1'], - dependencies: target_cortexm, - variables: { - 'description': 'WinChipHead CH579' - }, -) -all_targets += target_ch579 - -target_efm = declare_dependency( - sources: files( - 'efm32.c' - ) + efm32_stub, - compile_args: ['-DCONFIG_EFM32=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Energy Micro parts' - }, -) -all_targets += target_efm - -target_hc32 = declare_dependency( - sources: files('hc32l110.c'), - compile_args: ['-DCONFIG_HC32=1'], - dependencies: target_cortexm, - variables: { - 'description': 'HC32 parts' - }, -) -all_targets += target_hc32 - -target_lpc = declare_dependency( - sources: files( - 'lpc11xx.c', - 'lpc15xx.c', - 'lpc17xx.c', - 'lpc40xx.c', - 'lpc43xx.c', - 'lpc546xx.c', - 'lpc55xx.c', - 'lpc_common.c', - ), - compile_args: ['-DCONFIG_LPC=1'], - dependencies: target_cortexm, - variables: { - 'description': 'LPC series parts' - }, -) -all_targets += target_lpc - -target_nrf = declare_dependency( - sources: files( - 'nrf51.c', - 'nrf54l.c', - 'nrf91.c', - ), - compile_args: ['-DCONFIG_NRF=1'], - dependencies: target_cortexm, - variables: { - 'description': 'nRF series parts' - }, -) -all_targets += target_nrf - -target_nxp = declare_dependency( - sources: files( - 'imxrt.c', - 'kinetis.c', - 'nxpke04.c', - 's32k3xx.c', - ), - compile_args: ['-DCONFIG_NXP=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Kinetis series parts' - }, -) -all_targets += target_nxp - -target_puya = declare_dependency( - sources: files('puya.c'), - compile_args: ['-DCONFIG_PUYA=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Puya PY32 series parts' - }, -) -all_targets += target_puya - -target_renesas_ra = declare_dependency( - sources: files('renesas_ra.c'), - compile_args: ['-DCONFIG_RA=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Renesas RA parts' - }, -) -all_targets += target_renesas_ra - -target_renesas_rz = declare_dependency( - sources: files('renesas_rz.c'), - compile_args: ['-DCONFIG_RZ=1'], - dependencies: target_cortexar, - variables: { - 'description': 'Renesas RZ parts' - }, -) -all_targets += target_renesas_rz - -target_renesas = [target_renesas_ra, target_renesas_rz] - -target_rp = declare_dependency( - sources: files( - 'rp2040.c', - 'rp2350.c', - ) + rp2040_stub, - compile_args: ['-DCONFIG_RP=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Raspberry Pi MCUs (RP2040, RP2350)' - }, -) -all_targets += target_rp - -target_sam = declare_dependency( - sources: files( - 'sam3x.c', - 'sam4l.c', - 'samd.c', - 'samx5x.c', +targets += { + 'riscv32': declare_dependency( + sources: files('riscv32.c'), + dependencies: riscv_common, + variables: { + 'description': 'RISC-V 32-bit support' + }, + ) +} + +targets += { + 'riscv64': declare_dependency( + sources: files('riscv64.c'), + dependencies: riscv_common, + variables: { + 'description': 'RISC-V 64-bit support' + }, + ) +} + +targets += { + 'apollo3': declare_dependency( + sources: files('apollo3.c'), + compile_args: ['-DCONFIG_APOLLO3=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Ambiq Apollo3 parts' + }, + ) +} + +targets += { + 'ch579': declare_dependency( + sources: files('ch579.c'), + compile_args: ['-DCONFIG_CH579=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'WinChipHead CH579' + }, + ) +} + +targets += { + 'efm': declare_dependency( + sources: files( + 'efm32.c' + ) + efm32_stub, + compile_args: ['-DCONFIG_EFM32=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Energy Micro parts' + }, + ) +} + +targets += { + 'hc32': declare_dependency( + sources: files('hc32l110.c'), + compile_args: ['-DCONFIG_HC32=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'HC32 parts' + }, + ) +} + +targets += { + 'lpc': declare_dependency( + sources: files( + 'lpc11xx.c', + 'lpc15xx.c', + 'lpc17xx.c', + 'lpc40xx.c', + 'lpc43xx.c', + 'lpc546xx.c', + 'lpc55xx.c', + 'lpc_common.c', + ), + compile_args: ['-DCONFIG_LPC=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'LPC series parts' + }, + ) +} + +targets += { + 'nrf': declare_dependency( + sources: files( + 'nrf51.c', + 'nrf54l.c', + 'nrf91.c', + ), + compile_args: ['-DCONFIG_NRF=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'nRF series parts' + }, + ) +} + +targets += { + 'nxp': declare_dependency( + sources: files( + 'imxrt.c', + 'kinetis.c', + 'nxpke04.c', + 's32k3xx.c', + ), + compile_args: ['-DCONFIG_NXP=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Kinetis series parts' + }, + ) +} + +targets += { + 'puya': declare_dependency( + sources: files('puya.c'), + compile_args: ['-DCONFIG_PUYA=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Puya PY32 series parts' + }, + ) +} + +targets += { + 'renesas_ra': declare_dependency( + sources: files('renesas_ra.c'), + compile_args: ['-DCONFIG_RA=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Renesas RA parts' + }, ), - compile_args: ['-DCONFIG_SAM=1'], - dependencies: target_cortexm, - variables: { - 'description': 'ATSAM series parts' - }, -) -all_targets += target_sam + 'renesas_rz': declare_dependency( + sources: files('renesas_rz.c'), + compile_args: ['-DCONFIG_RZ=1'], + dependencies: targets['cortexar'], + variables: { + 'description': 'Renesas RZ parts' + }, + ) +} +targets += { + 'renesas': declare_dependency( + dependencies: [targets['renesas_ra'], targets['renesas_rz']], + variables: { + 'description': 'Renesas parts (RA + RZ)' + }, + ) +} + +targets += { + 'rp': declare_dependency( + sources: files( + 'rp2040.c', + 'rp2350.c', + ) + rp2040_stub, + compile_args: ['-DCONFIG_RP=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Raspberry Pi MCUs (RP2040, RP2350)' + }, + ) +} + +targets += { + 'sam': declare_dependency( + sources: files( + 'sam3x.c', + 'sam4l.c', + 'samd.c', + 'samx5x.c', + ), + compile_args: ['-DCONFIG_SAM=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'ATSAM series parts' + }, + ) +} stm_common = declare_dependency( sources: files( @@ -290,140 +303,142 @@ stm_common = declare_dependency( ) ) -target_stm32f1 = declare_dependency( - sources: files( - 'stm32f1.c', - ), - dependencies: [target_cortexm, stm_common], - variables: { - 'description': 'STM32F1 parts' - }, -) -all_targets += target_stm32f1 - -target_stm32f4 = declare_dependency( - sources: files( - 'stm32f4.c', +targets += { + 'stm32f1': declare_dependency( + sources: files( + 'stm32f1.c', + ), + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'STM32F1 parts' + }, ), - dependencies: [target_cortexm, stm_common], - variables: { - 'description': 'STM32F4 parts' - }, -) -all_targets += target_stm32f4 - -target_ch32 = declare_dependency( - sources: files( - 'ch32f1.c', - ), - compile_args: ['-DCONFIG_CH32=1'], - dependencies: target_stm32f1, - variables: { - 'description': 'WinChipHead CH32 ARM Cortex parts' - }, -) -all_targets += target_ch32 - -target_ch32v = declare_dependency( - sources: files( - 'ch32vx.c', - ), - dependencies: target_riscv32, - variables: { - 'description': 'WinChipHead CH32 RISC-V parts' - }, -) -all_targets += target_ch32v - -target_stm = declare_dependency( - sources: files( - 'stm32g0.c', - 'stm32h5.c', - 'stm32h7.c', - 'stm32l0.c', - 'stm32l4.c', - 'stm32mp15.c', - 'stm32wb0.c', - ), - compile_args: ['-DCONFIG_STM=1'], - dependencies: [target_cortexm, stm_common, target_stm32f1, target_stm32f4], - variables: { - 'description': 'STM32 parts' - }, -) -all_targets += target_stm - -target_gd32 = declare_dependency( - dependencies: [target_stm32f1, target_stm32f4], - compile_args: ['-DCONFIG_GD32=1'], - variables: { - 'description': 'GigaDevice parts' - }, -) -all_targets += target_gd32 - -target_gd32_rv = declare_dependency( - dependencies: [target_gd32, target_riscv32], - compile_args: ['-DCONFIG_GD32=1'], - variables: { - 'description': 'GigaDevice Risc-V parts' - }, -) -all_targets += target_gd32_rv - -target_mm32 = declare_dependency( - dependencies: target_stm32f1, - compile_args: ['-DCONFIG_MM32=1'], - variables: { - 'description': 'MindMotion parts' - }, -) -all_targets += target_mm32 - -target_at32f4 = declare_dependency( - sources: files( - 'at32f43x.c', + 'stm32f4': declare_dependency( + sources: files( + 'stm32f4.c', + ), + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'STM32F4 parts' + }, + ) +} + +targets += { + 'ch32': declare_dependency( + sources: files( + 'ch32f1.c', + ), + compile_args: ['-DCONFIG_CH32=1'], + dependencies: targets['stm32f1'], + variables: { + 'description': 'WinChipHead CH32 ARM Cortex parts' + }, ), - compile_args: ['-DCONFIG_AT32=1'], - dependencies: [target_cortexm, stm_common], - variables: { - 'description': 'Arterytek parts' - }, -) -all_targets += target_at32f4 - -target_ti = declare_dependency( - sources: files( - 'lmi.c', - 'msp432e4.c', - 'msp432p4.c', - 'mspm0.c' - ) + lmi_stub, - compile_args: ['-DCONFIG_TI=1'], - dependencies: target_cortexm, - variables: { - 'description': 'Texas Instruments parts' - }, -) -all_targets += target_ti - -target_xilinx = declare_dependency( - sources: files( - 'zynq7000.c', + 'ch32v': declare_dependency( + sources: files( + 'ch32vx.c', + ), + dependencies: targets['riscv32'], + variables: { + 'description': 'WinChipHead CH32 RISC-V parts' + }, + ) +} + +targets += { + 'stm': declare_dependency( + sources: files( + 'stm32g0.c', + 'stm32h5.c', + 'stm32h7.c', + 'stm32l0.c', + 'stm32l4.c', + 'stm32mp15.c', + 'stm32wb0.c', + ), + compile_args: ['-DCONFIG_STM=1'], + dependencies: [targets['cortexm'], stm_common, targets['stm32f1'], targets['stm32f4']], + variables: { + 'description': 'STM32 parts' + }, + ) +} + +targets += { + 'gd32': declare_dependency( + dependencies: [targets['stm32f1'], targets['stm32f4']], + compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice parts' + }, ), - dependencies: target_cortexar, - compile_args: ['-DCONFIG_XILINX=1'], - variables: { - 'description': 'Xilinx parts' - }, -) -all_targets += target_xilinx + 'gd32_rv': declare_dependency( + dependencies: [targets['riscv32'], targets['stm32f1'], targets['stm32f4']], + compile_args: ['-DCONFIG_GD32=1'], + variables: { + 'description': 'GigaDevice Risc-V parts' + }, + ) +} + +targets += { + 'mm32': declare_dependency( + dependencies: targets['stm32f1'], + compile_args: ['-DCONFIG_MM32=1'], + variables: { + 'description': 'MindMotion parts' + }, + ) +} + +targets += { + 'at32f4': declare_dependency( + sources: files( + 'at32f43x.c', + ), + compile_args: ['-DCONFIG_AT32=1'], + dependencies: [targets['cortexm'], stm_common], + variables: { + 'description': 'Arterytek parts' + }, + ) +} + +targets += { + 'ti': declare_dependency( + sources: files( + 'lmi.c', + 'msp432e4.c', + 'msp432p4.c', + 'mspm0.c' + ) + lmi_stub, + compile_args: ['-DCONFIG_TI=1'], + dependencies: targets['cortexm'], + variables: { + 'description': 'Texas Instruments parts' + }, + ) +} + +targets += { + 'xilinx': declare_dependency( + sources: files( + 'zynq7000.c', + ), + dependencies: targets['cortexar'], + compile_args: ['-DCONFIG_XILINX=1'], + variables: { + 'description': 'Xilinx parts' + }, + ) +} if is_firmware_build # Convert targets option list into a list of dependencies enabled_bmd_targets = [] - foreach target : get_option('targets') - enabled_bmd_targets += get_variable(f'target_@target@') + foreach target_name : get_option('targets') + enabled_bmd_targets += targets[target_name] endforeach # Check that at least one target is enabled @@ -443,6 +458,10 @@ if is_firmware_build endif # Define the libbmd target dependency, enable all architectures and targets +all_targets = [] +foreach target_name, target_dep : targets + all_targets += target_dep +endforeach libbmd_targets = declare_dependency( include_directories: target_common_includes, sources: target_common_sources, @@ -452,12 +471,10 @@ libbmd_targets = declare_dependency( if is_firmware_build # Build a dictionary of the targets that have been selected for the firmware build target_summary = {} - foreach target : all_targets - # Get the target description - target_description = target.get_variable('description') - - # Add the target enabled status to the summary - target_summary += {target_description: target in enabled_bmd_targets} + foreach target_name, target_dep : targets + # Get the target description and add the enabled status to the summary + target_description = target_dep.get_variable('description') + target_summary += {target_description: target_dep in enabled_bmd_targets} endforeach # Include the target enable list in the summary output