[Bug]: VGA emulation does not correctly emulate Chain Odd/Even on writes

[logiclrd]

Version

trunk/main

Host OS Type

Windows

Host OS name + version

Windows 10 Version 22H2 (Build 19045.6332)

Host Architecture

x86

Guest OS Type

other

Guest Architecture

x86

Guest OS name + version

MS-DOS 6.22

Component

Other

What happened?

A program which rewrites the VGA text mode font for graphical purposes had a bug in it. I didn't know that it had a bug in it, because it appeared to work when running inside a VirtualBox VM. However, under DOSBox-X and on real hardware, the bug became apparent. The program was setting the Sequencer register "Odd/Even Host Memory Write Adressing Disable", then mapping plane 2 to B800:0000 and writing font bitmap data. This seemed to work perfectly, but it turns out that on actual hardware, this register bit is only in charge of which plane writes go to. The address is still masked based on the value of the Graphics Controller Misc Graphics register, specifically the "Chain Odd/Even" field.

How can we reproduce this?

1. Set up a 16-bit DOS VM. Install MS-DOS 6.2 and QuickBASIC 4.5 or 7.1.

2. Transfer the following version of PIPELINE.BAS into the VM (e.g. via a floppy disk image):

https://github.com/logiclrd/QBX/blob/14f3b0c727a3fd06abcc65129558111b7803c8fe/Samples/PIPELINE.BAS

3. Run QuickBASIC, load PIPELINE.BAS and run it.

Expected

This version of PIPELINE.BAS contains a bug. It should produce output that looks like this:

Actual

VirtualBox displays output inconsistent with the proper operation of the VGA chipset, and which makes it look like PIPELINE.BAS does not contain a bug:

Did you upload all of your necessary log files, screenshots, etc.?

• Yes, I've uploaded all pertinent files to this issue.

[logiclrd]

I've been working with the author of DOSBox-X on this, and the understanding I've come to is that:

• The address bit masking/redirection described for Graphics Controller register 6 "Misc Graphics" bit 1 "Chain Odd/Even" applies regardless of whether the Sequencer's "Host Odd/Even Write" is enabled.
• The plane selection described for Sequencer register 4 "Memory Mode" bit 2 "Odd/Even Host Memory Write Addressing Disable" (when it's 0 and thus not disabled) applies regardless of whether the Graphics Controller's "Chain Odd/Even" is enabled.

This only applies when "Chain 4" isn't on, of course; in "Chain 4" mode, these bits are irrelevant.

The DOSBox-X author has a working 486 machine with a Western Digital/Paradise SVGA chipset and was very generous and ran the buggy version of my program on this actual hardware. Here's a screenshot, showing the bug with the same appearance as DOSBox-X's emulation:

I did some searching and I think the code in question is around these lines:

virtualbox/src/VBox/Devices/Graphics/DevVGA.cpp

Lines 1393 to 1394 in df331f2

	} else if (!(pThis->sr[4] & 0x04)) { /* Host access is controlled by SR4, not GR5! */
	/* odd/even mode (aka text mode mapping); GR4 does not affect writes! */