For STM32F303VC USART Clock source selection has wrong setting

[mathk]

From the datasheet of RM0316 (STM32F303xB/C/D/E/6/8)

The clock selection for USART1 has the following definition:

Bits 1:0 USART1SW[1:0]: USART1 clock source selection
    This bit is set and cleared by software to select the USART1 clock source.
    00: PCLK selected as USART1 clock source (default)
    01: System clock (SYSCLK) selected as USART1 clock
    10: LSE clock selected as USART1 clock
    11: HSI clock selected as USART1 clock

While in the clock config enum is:

pub const Usart1ClockSelectionList = enum {
    RCC_USART1CLKSOURCE_SYSCLK,
    RCC_USART1CLKSOURCE_HSI,
    RCC_USART1CLKSOURCE_LSE,
    RCC_USART1CLKSOURCE_PCLK1,
    RCC_USART1CLKSOURCE_PCLK2,
    pub fn get(self: @This()) usize {
        return switch (self) {
            .RCC_USART1CLKSOURCE_SYSCLK => 0,
            .RCC_USART1CLKSOURCE_HSI => 1,
            .RCC_USART1CLKSOURCE_LSE => 2,
            .RCC_USART1CLKSOURCE_PCLK1 => 3,
            .RCC_USART1CLKSOURCE_PCLK2 => 3,
        };
    }
};

None of the @enumFromInt nor .get() will provide the correct setting for the RCC.CFGR register.
The same situation happen for other USART clock selection list.

[RecursiveError]

Sorry for the delayed response.
This is a very common issue with multiplexers in almost all clock trees. I’m still thinking about a good way to correlate clock tree information with the actual hardware configuration.

At the moment, get() simply returns the index of the input node in a list defined by the peripheral. The ordering itself is arbitrary, and any cases where the configuration happens to match the hardware directly are purely coincidental.

[mathk]

I am not familiar with you code source but can it be envisage to not generate those enum and instead use the embassy regz generated one?