From 1a47871852fad82062db856130e8c56b2bbda86e Mon Sep 17 00:00:00 2001 From: luyong6 Date: Sun, 1 Mar 2020 16:14:38 +0100 Subject: [PATCH 1/4] add refclk300 for 9H7 Signed-off-by: luyong6 --- AD9H3/xdc/refclk300.xdc | 9 +++++++++ AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v | 7 +++++-- .../hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv | 1 + AD9H7/xdc/refclk300.xdc | 9 +++++++++ AD9V3/xdc/refclk300.xdc | 9 +++++++++ 5 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 AD9H3/xdc/refclk300.xdc create mode 100644 AD9H7/xdc/refclk300.xdc create mode 100644 AD9V3/xdc/refclk300.xdc diff --git a/AD9H3/xdc/refclk300.xdc b/AD9H3/xdc/refclk300.xdc new file mode 100644 index 0000000..aab4921 --- /dev/null +++ b/AD9H3/xdc/refclk300.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN AP26 [get_ports {refclk300_p}] +set_property IOSTANDARD LVDS [get_ports {refclk300_p}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] + +set_property PACKAGE_PIN AP27 [get_ports {refclk300_n}] +set_property IOSTANDARD LVDS [get_ports {refclk300_n}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] + +create_clock -period 3.333 -name refclk [get_ports {refclk300_p}] diff --git a/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v b/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v index 8096aba..955739c 100644 --- a/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v +++ b/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input refclk300 ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v @@ -45,11 +46,13 @@ module flash_vpd_wrapper ( // Flash Subsystem // //============================================================================= - wire spi_clk; // 100Mhz + wire spi_clk; + // 150Mhz BUFGCE_DIV #(.BUFGCE_DIVIDE(2)) spi_clk_inst ( - .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(clock_afu) + .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(refclk300) ); + flash_sub_system FLASH ( // -- Outputs diff --git a/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv b/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv index 461c96a..d498965 100644 --- a/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv +++ b/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input refclk300 ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v diff --git a/AD9H7/xdc/refclk300.xdc b/AD9H7/xdc/refclk300.xdc new file mode 100644 index 0000000..698185e --- /dev/null +++ b/AD9H7/xdc/refclk300.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN BJ52 [get_ports {refclk300_p}] +set_property IOSTANDARD LVDS [get_ports {refclk300_p}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] + +set_property PACKAGE_PIN BJ53 [get_ports {refclk300_n}] +set_property IOSTANDARD LVDS [get_ports {refclk300_n}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] + +create_clock -period 3.333 -name refclk [get_ports {refclk300_p}] diff --git a/AD9V3/xdc/refclk300.xdc b/AD9V3/xdc/refclk300.xdc new file mode 100644 index 0000000..aab4921 --- /dev/null +++ b/AD9V3/xdc/refclk300.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN AP26 [get_ports {refclk300_p}] +set_property IOSTANDARD LVDS [get_ports {refclk300_p}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] + +set_property PACKAGE_PIN AP27 [get_ports {refclk300_n}] +set_property IOSTANDARD LVDS [get_ports {refclk300_n}] +set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] + +create_clock -period 3.333 -name refclk [get_ports {refclk300_p}] From c16b18a5700e40315d04153dbfd79b50b937480a Mon Sep 17 00:00:00 2001 From: luyong6 Date: Tue, 3 Mar 2020 06:46:36 +0100 Subject: [PATCH 2/4] add a port clock_board_ref Signed-off-by: luyong6 --- AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v | 1 + AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv | 1 + AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v | 8 ++++---- AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv | 2 +- AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v | 1 + AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv | 1 + 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v b/AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v index 8096aba..53cabb9 100644 --- a/AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v +++ b/AD9H3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v diff --git a/AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv b/AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv index 461c96a..2908f1c 100644 --- a/AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv +++ b/AD9H3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v diff --git a/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v b/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v index 955739c..7a361f0 100644 --- a/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v +++ b/AD9H7/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v @@ -4,7 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx - ,input refclk300 + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v @@ -47,9 +47,9 @@ module flash_vpd_wrapper ( // //============================================================================= wire spi_clk; - // 150Mhz - BUFGCE_DIV #(.BUFGCE_DIVIDE(2)) spi_clk_inst ( - .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(refclk300) + // 100Mhz + BUFGCE_DIV #(.BUFGCE_DIVIDE(3)) spi_clk_inst ( + .O(spi_clk), .CE(1'b1), .CLR(1'b0), .I(clock_board_ref) ); diff --git a/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv b/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv index d498965..2908f1c 100644 --- a/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv +++ b/AD9H7/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv @@ -4,7 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx - ,input refclk300 + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v diff --git a/AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v b/AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v index 8096aba..53cabb9 100644 --- a/AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v +++ b/AD9V3/hdl/flash_vpd_wrapper/flash_vpd_wrapper.v @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v diff --git a/AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv b/AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv index ad494e3..8413af2 100644 --- a/AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv +++ b/AD9V3/hdl/flash_vpd_wrapper/sim_only/flash_vpd_wrapper.sv @@ -4,6 +4,7 @@ module flash_vpd_wrapper ( input clock_afu ,input clock_tlx + ,input clock_board_ref ,input reset_afu_n ,inout FPGA_FLASH_CE2_L // To/From FLASH of flash_sub_system.v ,inout FPGA_FLASH_DQ4 // To/From FLASH of flash_sub_system.v From 333b20033022671c405b96b33b928b85f15771de Mon Sep 17 00:00:00 2001 From: luyong6 Date: Tue, 3 Mar 2020 09:14:20 +0100 Subject: [PATCH 3/4] fix AD9H3 refclk300 Signed-off-by: luyong6 --- AD9H3/xdc/refclk300.xdc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/AD9H3/xdc/refclk300.xdc b/AD9H3/xdc/refclk300.xdc index aab4921..a2755da 100644 --- a/AD9H3/xdc/refclk300.xdc +++ b/AD9H3/xdc/refclk300.xdc @@ -1,9 +1,9 @@ -set_property PACKAGE_PIN AP26 [get_ports {refclk300_p}] +set_property PACKAGE_PIN AY31 [get_ports {refclk300_p}] set_property IOSTANDARD LVDS [get_ports {refclk300_p}] set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] -set_property PACKAGE_PIN AP27 [get_ports {refclk300_n}] +set_property PACKAGE_PIN BA31 [get_ports {refclk300_n}] set_property IOSTANDARD LVDS [get_ports {refclk300_n}] set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] -create_clock -period 3.333 -name refclk [get_ports {refclk300_p}] +create_clock -period 3.333 -name refclk [get_ports {refclk300_p} From 15a9d0d868d8f3cfd88cc0ff1304fe3f6d97be6d Mon Sep 17 00:00:00 2001 From: luyong6 Date: Tue, 10 Mar 2020 04:26:29 +0100 Subject: [PATCH 4/4] remove refclk300 xdc files because refclk300 are also freerun clks used by phy Signed-off-by: luyong6 --- AD9H3/xdc/refclk300.xdc | 9 --------- AD9H7/xdc/refclk300.xdc | 9 --------- AD9V3/xdc/refclk300.xdc | 9 --------- 3 files changed, 27 deletions(-) delete mode 100644 AD9H3/xdc/refclk300.xdc delete mode 100644 AD9H7/xdc/refclk300.xdc delete mode 100644 AD9V3/xdc/refclk300.xdc diff --git a/AD9H3/xdc/refclk300.xdc b/AD9H3/xdc/refclk300.xdc deleted file mode 100644 index a2755da..0000000 --- a/AD9H3/xdc/refclk300.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN AY31 [get_ports {refclk300_p}] -set_property IOSTANDARD LVDS [get_ports {refclk300_p}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] - -set_property PACKAGE_PIN BA31 [get_ports {refclk300_n}] -set_property IOSTANDARD LVDS [get_ports {refclk300_n}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] - -create_clock -period 3.333 -name refclk [get_ports {refclk300_p} diff --git a/AD9H7/xdc/refclk300.xdc b/AD9H7/xdc/refclk300.xdc deleted file mode 100644 index 698185e..0000000 --- a/AD9H7/xdc/refclk300.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN BJ52 [get_ports {refclk300_p}] -set_property IOSTANDARD LVDS [get_ports {refclk300_p}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] - -set_property PACKAGE_PIN BJ53 [get_ports {refclk300_n}] -set_property IOSTANDARD LVDS [get_ports {refclk300_n}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] - -create_clock -period 3.333 -name refclk [get_ports {refclk300_p}] diff --git a/AD9V3/xdc/refclk300.xdc b/AD9V3/xdc/refclk300.xdc deleted file mode 100644 index aab4921..0000000 --- a/AD9V3/xdc/refclk300.xdc +++ /dev/null @@ -1,9 +0,0 @@ -set_property PACKAGE_PIN AP26 [get_ports {refclk300_p}] -set_property IOSTANDARD LVDS [get_ports {refclk300_p}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_p}] - -set_property PACKAGE_PIN AP27 [get_ports {refclk300_n}] -set_property IOSTANDARD LVDS [get_ports {refclk300_n}] -set_property DIFF_TERM_ADV TERM_100 [get_ports {refclk300_n}] - -create_clock -period 3.333 -name refclk [get_ports {refclk300_p}]