diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v index c87b924..5bba0f4 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__100.00000______0.000______50.0______130.958_____98.575 +// clk_out2__200.00000______0.000______50.0______114.829_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo index 26aa6aa..f44f721 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__100.00000______0.000______50.0______130.958_____98.575 +// clk_out2__200.00000______0.000______50.0______114.829_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml index 7ea7dd2..775f901 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -1314,11 +1314,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4b09b841 + 9:7df132ee @@ -1333,11 +1333,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4b09b841 + 9:7df132ee @@ -1352,11 +1352,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1371,11 +1371,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1386,7 +1386,7 @@ outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1397,7 +1397,7 @@ outputProductCRC - 9:7e84de70 + 9:ea0c8e5a @@ -1411,11 +1411,11 @@ GENtimestamp - Fri Mar 13 05:23:39 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:0455ee43 @@ -1429,11 +1429,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1444,7 +1444,7 @@ outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1460,11 +1460,11 @@ GENtimestamp - Fri Mar 13 05:23:21 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -1478,11 +1478,11 @@ GENtimestamp - Fri Mar 13 05:23:22 UTC 2026 + Fri Mar 13 07:18:52 UTC 2026 outputProductCRC - 9:4111229a + 9:6e49cf90 @@ -2725,7 +2725,7 @@ C_OUTCLK_SUM_ROW2 - clk_out2__100.00000______0.000______50.0______130.958_____98.575 + clk_out2__200.00000______0.000______50.0______114.829_____98.575 C_OUTCLK_SUM_ROW3 @@ -2753,7 +2753,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 100.000 + 200.000 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2837,7 +2837,7 @@ C_CLKOUT2_OUT_FREQ - 100.00000 + 200.00000 C_CLKOUT3_OUT_FREQ @@ -3005,7 +3005,7 @@ C_MMCM_CLKOUT1_DIVIDE - 10 + 5 C_MMCM_CLKOUT2_DIVIDE @@ -3531,7 +3531,7 @@ C_DIVIDE2_AUTO - 0.25 + 0.125 C_DIVIDE3_AUTO @@ -3639,7 +3639,7 @@ C_CLKOUT1_ACTUAL_FREQ - 100.00000 + 200.00000 C_CLKOUT2_ACTUAL_FREQ @@ -4352,7 +4352,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 100.000 + 200.000 CLKOUT2_REQUESTED_PHASE @@ -4688,7 +4688,7 @@ MMCM_CLKOUT1_DIVIDE - 10 + 5 MMCM_CLKOUT1_DUTY_CYCLE @@ -4997,7 +4997,7 @@ CLKOUT2_JITTER Clkout2 Jitter - 130.958 + 114.829 CLKOUT2_PHASE_ERROR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v index 1b69f37..d319bf9 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__100.00000______0.000______50.0______130.958_____98.575 +// clk_out2__200.00000______0.000______50.0______114.829_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0; .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (10), + .CLKOUT1_DIVIDE (5), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v index 1651c3a..b25e7bc 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -2,10 +2,10 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 01:23:39 2026 +// Date : Fri Mar 13 02:38:01 2026 // Host : arya running 64-bit EndeavourOS Linux -// Command : write_verilog -force -mode funcsim -// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +// Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix +// clk_wiz_0_ clk_wiz_0_sim_netlist.v // Design : clk_wiz_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. @@ -32,7 +32,7 @@ module clk_wiz_0 wire locked; wire reset; - clk_wiz_0_clk_wiz inst + clk_wiz_0_clk_wiz_0_clk_wiz inst (.clk_in1(clk_in1), .clk_out1(clk_out1), .clk_out2(clk_out2), @@ -40,7 +40,7 @@ module clk_wiz_0 .reset(reset)); endmodule -module clk_wiz_0_clk_wiz +module clk_wiz_0_clk_wiz_0_clk_wiz (clk_out1, clk_out2, reset, @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(10), + .CLKOUT1_DIVIDE(5), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl index de421a2..f3a5f3c 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -2,10 +2,10 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 01:23:39 2026 +-- Date : Fri Mar 13 02:38:01 2026 -- Host : arya running 64-bit EndeavourOS Linux --- Command : write_vhdl -force -mode funcsim --- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +-- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix +-- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl -- Design : clk_wiz_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. @@ -15,7 +15,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; -entity clk_wiz_0_clk_wiz is +entity clk_wiz_0_clk_wiz_0_clk_wiz is port ( clk_out1 : out STD_LOGIC; clk_out2 : out STD_LOGIC; @@ -23,9 +23,9 @@ entity clk_wiz_0_clk_wiz is locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); -end clk_wiz_0_clk_wiz; +end clk_wiz_0_clk_wiz_0_clk_wiz; -architecture STRUCTURE of clk_wiz_0_clk_wiz is +architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is signal clk_in1_clk_wiz_0 : STD_LOGIC; signal clk_out1_clk_wiz_0 : STD_LOGIC; signal clk_out2_clk_wiz_0 : STD_LOGIC; @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 10, + CLKOUT1_DIVIDE => 5, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, @@ -187,7 +187,7 @@ end clk_wiz_0; architecture STRUCTURE of clk_wiz_0 is begin -inst: entity work.clk_wiz_0_clk_wiz +inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v index 585b16c..cc40900 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,10 +2,10 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 01:23:39 2026 +// Date : Fri Mar 13 02:38:01 2026 // Host : arya running 64-bit EndeavourOS Linux -// Command : write_verilog -force -mode synth_stub -// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +// Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix +// clk_wiz_0_ clk_wiz_0_stub.v // Design : clk_wiz_0 // Purpose : Stub declaration of top-level module interface // Device : xc7a35tcpg236-1 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index 34c896b..5515e7b 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,10 +2,10 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 01:23:39 2026 +-- Date : Fri Mar 13 02:38:01 2026 -- Host : arya running 64-bit EndeavourOS Linux --- Command : write_vhdl -force -mode synth_stub --- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix +-- clk_wiz_0_ clk_wiz_0_stub.vhdl -- Design : clk_wiz_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7a35tcpg236-1 diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo index 26aa6aa..f44f721 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__100.00000______0.000______50.0______130.958_____98.575 +// clk_out2__200.00000______0.000______50.0______114.829_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v deleted file mode 100644 index 585b16c..0000000 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -// -------------------------------------------------------------------------------- -// Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Fri Mar 13 01:23:39 2026 -// Host : arya running 64-bit EndeavourOS Linux -// Command : write_verilog -force -mode synth_stub -// /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v -// Design : clk_wiz_0 -// Purpose : Stub declaration of top-level module interface -// Device : xc7a35tcpg236-1 -// -------------------------------------------------------------------------------- - -// This empty module with port declaration file causes synthesis tools to infer a black box for IP. -// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. -// Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) -module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1) -/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ -/* synthesis syn_force_seq_prim="clk_out1" */ -/* synthesis syn_force_seq_prim="clk_out2" */; - output clk_out1 /* synthesis syn_isclock = 1 */; - output clk_out2 /* synthesis syn_isclock = 1 */; - input reset; - output locked; - input clk_in1; -endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl deleted file mode 100644 index 34c896b..0000000 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ /dev/null @@ -1,35 +0,0 @@ --- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --- -------------------------------------------------------------------------------- --- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Fri Mar 13 01:23:39 2026 --- Host : arya running 64-bit EndeavourOS Linux --- Command : write_vhdl -force -mode synth_stub --- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl --- Design : clk_wiz_0 --- Purpose : Stub declaration of top-level module interface --- Device : xc7a35tcpg236-1 --- -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; - -entity clk_wiz_0 is - Port ( - clk_out1 : out STD_LOGIC; - clk_out2 : out STD_LOGIC; - reset : in STD_LOGIC; - locked : out STD_LOGIC; - clk_in1 : in STD_LOGIC - ); - - attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; -end clk_wiz_0; - -architecture stub of clk_wiz_0 is - attribute syn_black_box : boolean; - attribute black_box_pad_pin : string; - attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; -begin -end; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh index 8979a61..3f46253 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh index 75c07c1..03f7951 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh index 8d68349..5d50237 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh index c16976b..0c8da79 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh index d61eba1..5472820 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt index 83abdbe..63015d2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 +# Generated by export_simulation on Fri Mar 13 03:18:53 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh index f1954b3..9ac4270 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 +# Script generated by Vivado on Fri Mar 13 03:18:53 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc index d6202ee..b7cba73 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc @@ -1,8 +1,6 @@ ## Clock set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] -set_clock_groups -asynchronous \ - -group [get_clocks -include_generated_clocks clk_25] ## Reset (btnC) set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC] set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU] diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index 56510d1..537c13a 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -87,7 +87,7 @@ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -171,7 +171,7 @@ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -247,7 +247,7 @@ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "130.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "114.829", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -339,14 +339,14 @@ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__100.00000______0.000______50.0______130.958_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__200.00000______0.000______50.0______114.829_____98.575", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -367,7 +367,7 @@ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -409,7 +409,7 @@ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,7 +540,7 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.125", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE3_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE4_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE5_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], @@ -567,7 +567,7 @@ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "200.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], @@ -686,5 +686,5 @@ } } }, - "checksum": "1dfc4686" + "checksum": "2ec823c6" } \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 128abb8..11d04dd 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -66,12 +66,12 @@