diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v index c1b4390..c87b924 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -53,7 +53,8 @@ // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- -// clk_out1__25.00000______0.000______50.0______181.828____104.359 +// clk_out1__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__100.00000______0.000______50.0______130.958_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -62,12 +63,13 @@ `timescale 1ps/1ps -(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) module clk_wiz_0 ( // Clock out ports output clk_out1, + output clk_out2, // Status and control signals input reset, output locked, @@ -79,6 +81,7 @@ module clk_wiz_0 ( // Clock out ports .clk_out1(clk_out1), + .clk_out2(clk_out2), // Status and control signals .reset(reset), .locked(locked), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo index 086388b..26aa6aa 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -52,7 +52,8 @@ // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- -// clk_out1__25.00000______0.000______50.0______181.828____104.359 +// clk_out1__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__100.00000______0.000______50.0______130.958_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -69,6 +70,7 @@ ( // Clock out ports .clk_out1(clk_out1), // output clk_out1 + .clk_out2(clk_out2), // output clk_out2 // Status and control signals .reset(reset), // input reset .locked(locked), // output locked diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml index 49c8b39..7ea7dd2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -1210,6 +1210,96 @@ + + clock_CLK_OUT2 + + + + + + + CLK_OUT2 + + + clk_out2 + + + + + + FREQ_HZ + 100000000 + + + none + + + + + FREQ_TOLERANCE_HZ + 0 + + + none + + + + + PHASE + 0.0 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_PORT + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + INSERT_VIP + 0 + + + simulation.rtl + + + + + @@ -1224,11 +1314,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:00fdc114 + 9:4b09b841 @@ -1243,11 +1333,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:00fdc114 + 9:4b09b841 @@ -1262,11 +1352,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -1281,11 +1371,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -1296,7 +1386,7 @@ outputProductCRC - 9:dd394782 + 9:4111229a @@ -1307,7 +1397,7 @@ outputProductCRC - 9:424814e7 + 9:7e84de70 @@ -1321,11 +1411,11 @@ GENtimestamp - Wed Mar 11 20:44:32 UTC 2026 + Fri Mar 13 05:23:39 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -1339,11 +1429,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -1354,7 +1444,7 @@ outputProductCRC - 9:dd394782 + 9:4111229a @@ -1370,11 +1460,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:21 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -1388,11 +1478,11 @@ GENtimestamp - Wed Mar 11 20:44:14 UTC 2026 + Fri Mar 13 05:23:22 UTC 2026 outputProductCRC - 9:dd394782 + 9:4111229a @@ -2308,6 +2398,19 @@ + + clk_out2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + locked @@ -2325,7 +2428,7 @@ C_CLKOUT2_USED - 0 + 1 C_USER_CLK_FREQ0 @@ -2565,7 +2668,7 @@ C_NUM_OUT_CLKS - 1 + 2 C_CLKOUT1_DRIVES @@ -2618,11 +2721,11 @@ C_OUTCLK_SUM_ROW1 - clk_out1__25.00000______0.000______50.0______181.828____104.359 + clk_out1__25.00000______0.000______50.0______175.402_____98.575 C_OUTCLK_SUM_ROW2 - no_CLK_OUT2_output + clk_out2__100.00000______0.000______50.0______130.958_____98.575 C_OUTCLK_SUM_ROW3 @@ -2650,7 +2753,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 25.000 + 100.000 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2734,7 +2837,7 @@ C_CLKOUT2_OUT_FREQ - 25.00000 + 100.00000 C_CLKOUT3_OUT_FREQ @@ -2858,7 +2961,7 @@ C_MMCM_CLKFBOUT_MULT_F - 9.125 + 10.000 C_MMCM_CLKIN1_PERIOD @@ -2898,11 +3001,11 @@ C_MMCM_CLKOUT0_DIVIDE_F - 36.500 + 40.000 C_MMCM_CLKOUT1_DIVIDE - 1 + 10 C_MMCM_CLKOUT2_DIVIDE @@ -3428,27 +3531,27 @@ C_DIVIDE2_AUTO - 0.0273972602739726 + 0.25 C_DIVIDE3_AUTO - 0.0273972602739726 + 0.025 C_DIVIDE4_AUTO - 0.0273972602739726 + 0.025 C_DIVIDE5_AUTO - 0.0273972602739726 + 0.025 C_DIVIDE6_AUTO - 0.0273972602739726 + 0.025 C_DIVIDE7_AUTO - 0.0273972602739726 + 0.025 C_PLLBUFGCEDIV @@ -3536,7 +3639,7 @@ C_CLKOUT1_ACTUAL_FREQ - 25.00000 + 100.00000 C_CLKOUT2_ACTUAL_FREQ @@ -4105,7 +4208,7 @@ CLKOUT2_USED - false + true CLKOUT3_USED @@ -4129,7 +4232,7 @@ NUM_OUT_CLKS - 1 + 2 CLK_OUT1_USE_FINE_PS_GUI @@ -4249,7 +4352,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 25.000 + 100.000 CLKOUT2_REQUESTED_PHASE @@ -4525,7 +4628,7 @@ MMCM_CLKFBOUT_MULT_F - 9.125 + 10.000 MMCM_CLKFBOUT_PHASE @@ -4569,7 +4672,7 @@ MMCM_CLKOUT0_DIVIDE_F - 36.500 + 40.000 MMCM_CLKOUT0_DUTY_CYCLE @@ -4585,7 +4688,7 @@ MMCM_CLKOUT1_DIVIDE - 1 + 10 MMCM_CLKOUT1_DUTY_CYCLE @@ -4884,17 +4987,17 @@ CLKOUT1_JITTER Clkout1 Jitter - 181.828 + 175.402 CLKOUT1_PHASE_ERROR Clkout1 Phase - 104.359 + 98.575 CLKOUT2_JITTER Clkout2 Jitter - 175.402 + 130.958 CLKOUT2_PHASE_ERROR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v index 034bdd5..1b69f37 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -53,7 +53,8 @@ // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- -// clk_out1__25.00000______0.000______50.0______181.828____104.359 +// clk_out1__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__100.00000______0.000______50.0______130.958_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -67,6 +68,7 @@ module clk_wiz_0_clk_wiz (// Clock in ports // Clock out ports output clk_out1, + output clk_out2, // Status and control signals input reset, output locked, @@ -107,7 +109,6 @@ wire clk_in2_clk_wiz_0; wire clkfbout_buf_clk_wiz_0; wire clkfboutb_unused; wire clkout0b_unused; - wire clkout1_unused; wire clkout1b_unused; wire clkout2_unused; wire clkout2b_unused; @@ -126,13 +127,17 @@ wire clk_in2_clk_wiz_0; .COMPENSATION ("ZHOLD"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (1), - .CLKFBOUT_MULT_F (9.125), + .CLKFBOUT_MULT_F (10.000), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (36.500), + .CLKOUT0_DIVIDE_F (40.000), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (10), + .CLKOUT1_PHASE (0.000), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (10.000)) mmcm_adv_inst // Output clocks @@ -141,7 +146,7 @@ wire clk_in2_clk_wiz_0; .CLKFBOUTB (clkfboutb_unused), .CLKOUT0 (clk_out1_clk_wiz_0), .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), + .CLKOUT1 (clk_out2_clk_wiz_0), .CLKOUT1B (clkout1b_unused), .CLKOUT2 (clkout2_unused), .CLKOUT2B (clkout2b_unused), @@ -197,6 +202,10 @@ wire clk_in2_clk_wiz_0; .I (clk_out1_clk_wiz_0)); + BUFG clkout2_buf + (.O (clk_out2), + .I (clk_out2_clk_wiz_0)); + endmodule diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v index 81a24ee..1651c3a 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Wed Mar 11 16:44:32 2026 +// Date : Fri Mar 13 01:23:39 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode funcsim // /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -16,32 +16,38 @@ (* NotValidForBitStream *) module clk_wiz_0 (clk_out1, + clk_out2, reset, locked, clk_in1); output clk_out1; + output clk_out2; input reset; output locked; input clk_in1; (* IBUF_LOW_PWR *) wire clk_in1; wire clk_out1; + wire clk_out2; wire locked; wire reset; clk_wiz_0_clk_wiz inst (.clk_in1(clk_in1), .clk_out1(clk_out1), + .clk_out2(clk_out2), .locked(locked), .reset(reset)); endmodule module clk_wiz_0_clk_wiz (clk_out1, + clk_out2, reset, locked, clk_in1); output clk_out1; + output clk_out2; input reset; output locked; input clk_in1; @@ -50,6 +56,8 @@ module clk_wiz_0_clk_wiz wire clk_in1_clk_wiz_0; wire clk_out1; wire clk_out1_clk_wiz_0; + wire clk_out2; + wire clk_out2_clk_wiz_0; wire clkfbout_buf_clk_wiz_0; wire clkfbout_clk_wiz_0; wire locked; @@ -58,7 +66,6 @@ module clk_wiz_0_clk_wiz wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED; - wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED; wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED; @@ -89,18 +96,22 @@ module clk_wiz_0_clk_wiz (.I(clk_out1_clk_wiz_0), .O(clk_out1)); (* BOX_TYPE = "PRIMITIVE" *) + BUFG clkout2_buf + (.I(clk_out2_clk_wiz_0), + .O(clk_out2)); + (* BOX_TYPE = "PRIMITIVE" *) MMCME2_ADV #( .BANDWIDTH("OPTIMIZED"), - .CLKFBOUT_MULT_F(9.125000), + .CLKFBOUT_MULT_F(10.000000), .CLKFBOUT_PHASE(0.000000), .CLKFBOUT_USE_FINE_PS("FALSE"), .CLKIN1_PERIOD(10.000000), .CLKIN2_PERIOD(0.000000), - .CLKOUT0_DIVIDE_F(36.500000), + .CLKOUT0_DIVIDE_F(40.000000), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(1), + .CLKOUT1_DIVIDE(10), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), @@ -149,7 +160,7 @@ module clk_wiz_0_clk_wiz .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED), .CLKOUT0(clk_out1_clk_wiz_0), .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED), - .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED), + .CLKOUT1(clk_out2_clk_wiz_0), .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED), .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED), .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl index cbf9055..de421a2 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Wed Mar 11 16:44:32 2026 +-- Date : Fri Mar 13 01:23:39 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode funcsim -- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -18,6 +18,7 @@ use UNISIM.VCOMPONENTS.ALL; entity clk_wiz_0_clk_wiz is port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC @@ -27,13 +28,13 @@ end clk_wiz_0_clk_wiz; architecture STRUCTURE of clk_wiz_0_clk_wiz is signal clk_in1_clk_wiz_0 : STD_LOGIC; signal clk_out1_clk_wiz_0 : STD_LOGIC; + signal clk_out2_clk_wiz_0 : STD_LOGIC; signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; signal clkfbout_clk_wiz_0 : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; - signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; @@ -55,6 +56,7 @@ architecture STRUCTURE of clk_wiz_0_clk_wiz is attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; + attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG @@ -75,19 +77,24 @@ clkout1_buf: unisim.vcomponents.BUFG I => clk_out1_clk_wiz_0, O => clk_out1 ); +clkout2_buf: unisim.vcomponents.BUFG + port map ( + I => clk_out2_clk_wiz_0, + O => clk_out2 + ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", - CLKFBOUT_MULT_F => 9.125000, + CLKFBOUT_MULT_F => 10.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, - CLKOUT0_DIVIDE_F => 36.500000, + CLKOUT0_DIVIDE_F => 40.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 1, + CLKOUT1_DIVIDE => 10, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, @@ -137,7 +144,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk_out1_clk_wiz_0, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, - CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED, + CLKOUT1 => clk_out2_clk_wiz_0, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, @@ -169,6 +176,7 @@ use UNISIM.VCOMPONENTS.ALL; entity clk_wiz_0 is port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC @@ -183,6 +191,7 @@ inst: entity work.clk_wiz_0_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, + clk_out2 => clk_out2, locked => locked, reset => reset ); diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v index c79fbeb..585b16c 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Wed Mar 11 16:44:32 2026 +// Date : Fri Mar 13 01:23:39 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode synth_stub // /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -14,11 +14,13 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) -module clk_wiz_0(clk_out1, reset, locked, clk_in1) +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1) /* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ -/* synthesis syn_force_seq_prim="clk_out1" */; +/* synthesis syn_force_seq_prim="clk_out1" */ +/* synthesis syn_force_seq_prim="clk_out2" */; output clk_out1 /* synthesis syn_isclock = 1 */; + output clk_out2 /* synthesis syn_isclock = 1 */; input reset; output locked; input clk_in1; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index a8189c4..34c896b 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Wed Mar 11 16:44:32 2026 +-- Date : Fri Mar 13 01:23:39 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode synth_stub -- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -16,19 +16,20 @@ use IEEE.STD_LOGIC_1164.ALL; entity clk_wiz_0 is Port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; + attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_wiz_0; architecture stub of clk_wiz_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; + attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; begin end; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo index 086388b..26aa6aa 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -52,7 +52,8 @@ // Output Output Phase Duty Cycle Pk-to-Pk Phase // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- -// clk_out1__25.00000______0.000______50.0______181.828____104.359 +// clk_out1__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__100.00000______0.000______50.0______130.958_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -69,6 +70,7 @@ ( // Clock out ports .clk_out1(clk_out1), // output clk_out1 + .clk_out2(clk_out2), // output clk_out2 // Status and control signals .reset(reset), // input reset .locked(locked), // output locked diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v index c79fbeb..585b16c 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Wed Mar 11 16:44:32 2026 +// Date : Fri Mar 13 01:23:39 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode synth_stub // /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -14,11 +14,13 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) -module clk_wiz_0(clk_out1, reset, locked, clk_in1) +(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) +module clk_wiz_0(clk_out1, clk_out2, reset, locked, clk_in1) /* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */ -/* synthesis syn_force_seq_prim="clk_out1" */; +/* synthesis syn_force_seq_prim="clk_out1" */ +/* synthesis syn_force_seq_prim="clk_out2" */; output clk_out1 /* synthesis syn_isclock = 1 */; + output clk_out2 /* synthesis syn_isclock = 1 */; input reset; output locked; input clk_in1; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index a8189c4..34c896b 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Wed Mar 11 16:44:32 2026 +-- Date : Fri Mar 13 01:23:39 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode synth_stub -- /home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -16,19 +16,20 @@ use IEEE.STD_LOGIC_1164.ALL; entity clk_wiz_0 is Port ( clk_out1 : out STD_LOGIC; + clk_out2 : out STD_LOGIC; reset : in STD_LOGIC; locked : out STD_LOGIC; clk_in1 : in STD_LOGIC ); attribute CORE_GENERATION_INFO : string; - attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; + attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v6_0_17_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_wiz_0; architecture stub of clk_wiz_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; - attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; + attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,reset,locked,clk_in1"; begin end; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh index a90d55d..8979a61 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh index e901369..75c07c1 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh index d662743..8d68349 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh index be6a5d0..c16976b 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh index ed1572a..d61eba1 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt index 1c77c7a..83abdbe 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Wed Mar 11 16:44:15 EDT 2026 +# Generated by export_simulation on Fri Mar 13 01:23:22 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh index 486c5b2..f1954b3 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Wed Mar 11 16:44:15 EDT 2026 +# Script generated by Vivado on Fri Mar 13 01:23:22 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index 9da8ffe..56510d1 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -51,13 +51,13 @@ "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "CLKOUT2_USED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "NUM_OUT_CLKS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -87,7 +87,7 @@ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -156,7 +156,7 @@ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], - "MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -167,11 +167,11 @@ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -245,9 +245,9 @@ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_JITTER": [ { "value": "181.828", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT1_PHASE_ERROR": [ { "value": "104.359", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "130.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -265,7 +265,7 @@ "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] }, "model_parameters": { - "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -325,7 +325,7 @@ "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_NUM_OUT_CLKS": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ], @@ -338,15 +338,15 @@ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______181.828____104.359", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__100.00000______0.000______50.0______130.958_____98.575", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -367,7 +367,7 @@ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -398,7 +398,7 @@ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ], @@ -408,8 +408,8 @@ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], - "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,12 +540,12 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE3_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE4_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE5_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE6_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE7_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE3_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE4_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE5_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE6_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE7_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], @@ -567,7 +567,7 @@ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], @@ -611,6 +611,7 @@ "reset": [ { "direction": "in", "driver_value": "0" } ], "clk_in1": [ { "direction": "in" } ], "clk_out1": [ { "direction": "out" } ], + "clk_out2": [ { "direction": "out" } ], "locked": [ { "direction": "out" } ] }, "interfaces": { @@ -663,9 +664,27 @@ "port_maps": { "CLK_OUT1": [ { "physical_name": "clk_out1" } ] } + }, + "clock_CLK_OUT2": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "master", + "parameters": { + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK_OUT2": [ { "physical_name": "clk_out2" } ] + } } } } }, - "checksum": "7c331cae" + "checksum": "1dfc4686" } \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v index cee8080..58bc133 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v @@ -18,12 +18,25 @@ module Top( // ------------------------------------------------------- // Clock divider: 100MHz -> 25MHz // ------------------------------------------------------- - reg [1:0] clk_div; - always @(posedge clk) begin - if (btnC) clk_div <= 2'h0; - else clk_div <= clk_div + 2'h1; - end - wire clk_25 = clk_div[1]; + wire cpu_clk; + wire clk_25; + wire locked; + clk_wiz_0 instance_name + ( + // Clock out ports + .clk_out1(clk_25), // output clk_out1 + .clk_out2(cpu_clk), // output clk_out2 + // Status and control signals + .reset(btnC), // input reset + .locked(locked), // output locked + .clk_in1(clk) // input clk_in1 + ); +// reg [1:0] clk_div; +// always @(posedge clk) begin +// if (btnC) clk_div <= 2'h0; +// else clk_div <= clk_div + 2'h1; +// end +// wire clk_25 = clk_div[1]; wire [3:0] btns = {btnU,btnR,btnL,btnD}; // ------------------------------------------------------- // UART program loader @@ -54,7 +67,7 @@ module Top( wire [31:0] debug_1, debug_2; Main cpu ( - .clock (clk), + .clock (cpu_clk), .reset (reset), .io_execute (execute), .io_debug_write (debug_write), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index 98baa2f..128abb8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -66,12 +66,12 @@