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mansrmstorsjo
mansr
authored and
mstorsjo
committed
stagefright aacenc: Fix inline asm
- don't write input-only registers - use temp variables instead of hardcoded regs - don't build constants manually, specify as asm inputs - remove unnecessary volatile qualifiers Change-Id: I3b9bb2d30768bcf409dc478bde4489135eeb50d7
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  • media/libstagefright/codecs/aacenc/basic_op

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‎media/libstagefright/codecs/aacenc/basic_op/basic_op.h‎

Lines changed: 61 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -228,7 +228,7 @@ Word32 L_shr_r (Word32 L_var1, Word16 var2);
228228
__inline Word32 ASM_L_shr(Word32 L_var1, Word16 var2)
229229
{
230230
Word32 result;
231-
asm volatile(
231+
asm (
232232
"MOV %[result], %[L_var1], ASR %[var2] \n"
233233
:[result]"=r"(result)
234234
:[L_var1]"r"(L_var1), [var2]"r"(var2)
@@ -239,26 +239,23 @@ __inline Word32 ASM_L_shr(Word32 L_var1, Word16 var2)
239239
__inline Word32 ASM_L_shl(Word32 L_var1, Word16 var2)
240240
{
241241
Word32 result;
242-
asm volatile(
243-
"MOV r2, %[L_var1] \n"
244-
"MOV r3, #0x7fffffff\n"
242+
asm (
245243
"MOV %[result], %[L_var1], ASL %[var2] \n"
246-
"TEQ r2, %[result], ASR %[var2]\n"
247-
"EORNE %[result],r3,r2,ASR#31\n"
244+
"TEQ %[L_var1], %[result], ASR %[var2]\n"
245+
"EORNE %[result], %[mask], %[L_var1], ASR #31\n"
248246
:[result]"=&r"(result)
249-
:[L_var1]"r"(L_var1), [var2]"r"(var2)
250-
:"r2", "r3"
247+
:[L_var1]"r"(L_var1), [var2]"r"(var2), [mask]"r"(0x7fffffff)
251248
);
252249
return result;
253250
}
254251

255252
__inline Word32 ASM_shr(Word32 L_var1, Word16 var2)
256253
{
257254
Word32 result;
258-
asm volatile(
255+
asm (
259256
"CMP %[var2], #15\n"
260-
"MOVGE %[var2], #15\n"
261-
"MOV %[result], %[L_var1], ASR %[var2]\n"
257+
"MOVLT %[result], %[L_var1], ASR %[var2]\n"
258+
"MOVGE %[result], %[L_var1], ASR #15\n"
262259
:[result]"=r"(result)
263260
:[L_var1]"r"(L_var1), [var2]"r"(var2)
264261
);
@@ -268,18 +265,16 @@ __inline Word32 ASM_shr(Word32 L_var1, Word16 var2)
268265
__inline Word32 ASM_shl(Word32 L_var1, Word16 var2)
269266
{
270267
Word32 result;
271-
asm volatile(
268+
Word32 tmp;
269+
asm (
272270
"CMP %[var2], #16\n"
273-
"MOVGE %[var2], #16\n"
274-
"MOV %[result], %[L_var1], ASL %[var2]\n"
275-
"MOV r3, #1\n"
276-
"MOV r2, %[result], ASR #15\n"
277-
"RSB r3,r3,r3,LSL #15 \n"
278-
"TEQ r2, %[result], ASR #31 \n"
279-
"EORNE %[result], r3, %[result],ASR #31"
280-
:[result]"=r"(result)
281-
:[L_var1]"r"(L_var1), [var2]"r"(var2)
282-
:"r2", "r3"
271+
"MOVLT %[result], %[L_var1], ASL %[var2]\n"
272+
"MOVGE %[result], %[L_var1], ASL #16\n"
273+
"MOV %[tmp], %[result], ASR #15\n"
274+
"TEQ %[tmp], %[result], ASR #31 \n"
275+
"EORNE %[result], %[mask], %[result],ASR #31"
276+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
277+
:[L_var1]"r"(L_var1), [var2]"r"(var2), [mask]"r"(0x7fff)
283278
);
284279
return result;
285280
}
@@ -295,16 +290,14 @@ __inline Word16 saturate(Word32 L_var1)
295290
{
296291
#if ARMV5TE_SAT
297292
Word16 result;
293+
Word32 tmp;
298294
asm volatile (
299-
"MOV r3, #1\n"
300-
"MOV r2,%[L_var1],ASR#15\n"
301-
"RSB r3, r3, r3, LSL #15\n"
302-
"TEQ r2,%[L_var1],ASR#31\n"
303-
"EORNE %[result],r3,%[L_var1],ASR#31\n"
295+
"MOV %[tmp], %[L_var1],ASR#15\n"
296+
"TEQ %[tmp], %[L_var1],ASR#31\n"
297+
"EORNE %[result], %[mask],%[L_var1],ASR#31\n"
304298
"MOVEQ %[result], %[L_var1]\n"
305-
:[result]"=r"(result)
306-
:[L_var1]"r"(L_var1)
307-
:"r2", "r3"
299+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
300+
:[L_var1]"r"(L_var1), [mask]"r"(0x7fff)
308301
);
309302

310303
return result;
@@ -420,7 +413,7 @@ __inline Word32 L_mult(Word16 var1, Word16 var2)
420413
{
421414
#if ARMV5TE_L_MULT
422415
Word32 result;
423-
asm volatile(
416+
asm (
424417
"SMULBB %[result], %[var1], %[var2] \n"
425418
"QADD %[result], %[result], %[result] \n"
426419
:[result]"=r"(result)
@@ -450,7 +443,7 @@ __inline Word32 L_msu (Word32 L_var3, Word16 var1, Word16 var2)
450443
{
451444
#if ARMV5TE_L_MSU
452445
Word32 result;
453-
asm volatile(
446+
asm (
454447
"SMULBB %[result], %[var1], %[var2] \n"
455448
"QADD %[result], %[result], %[result] \n"
456449
"QSUB %[result], %[L_var3], %[result]\n"
@@ -474,7 +467,7 @@ __inline Word32 L_sub(Word32 L_var1, Word32 L_var2)
474467
{
475468
#if ARMV5TE_L_SUB
476469
Word32 result;
477-
asm volatile(
470+
asm (
478471
"QSUB %[result], %[L_var1], %[L_var2]\n"
479472
:[result]"=r"(result)
480473
:[L_var1]"r"(L_var1), [L_var2]"r"(L_var2)
@@ -589,16 +582,14 @@ __inline Word16 add (Word16 var1, Word16 var2)
589582
{
590583
#if ARMV5TE_ADD
591584
Word32 result;
592-
asm volatile(
585+
Word32 tmp;
586+
asm (
593587
"ADD %[result], %[var1], %[var2] \n"
594-
"MOV r3, #0x1\n"
595-
"MOV r2, %[result], ASR #15\n"
596-
"RSB r3, r3, r3, LSL, #15\n"
597-
"TEQ r2, %[result], ASR #31\n"
598-
"EORNE %[result], r3, %[result], ASR #31"
599-
:[result]"=r"(result)
600-
:[var1]"r"(var1), [var2]"r"(var2)
601-
:"r2", "r3"
588+
"MOV %[tmp], %[result], ASR #15 \n"
589+
"TEQ %[tmp], %[result], ASR #31 \n"
590+
"EORNE %[result], %[mask], %[result], ASR #31"
591+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
592+
:[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff)
602593
);
603594
return result;
604595
#else
@@ -619,16 +610,14 @@ __inline Word16 sub(Word16 var1, Word16 var2)
619610
{
620611
#if ARMV5TE_SUB
621612
Word32 result;
622-
asm volatile(
623-
"MOV r3, #1\n"
613+
Word32 tmp;
614+
asm (
624615
"SUB %[result], %[var1], %[var2] \n"
625-
"RSB r3,r3,r3,LSL#15\n"
626-
"MOV r2, %[var1], ASR #15 \n"
627-
"TEQ r2, %[var1], ASR #31 \n"
628-
"EORNE %[result], r3, %[result], ASR #31 \n"
629-
:[result]"=&r"(result)
630-
:[var1]"r"(var1), [var2]"r"(var2)
631-
:"r2", "r3"
616+
"MOV %[tmp], %[var1], ASR #15 \n"
617+
"TEQ %[tmp], %[var1], ASR #31 \n"
618+
"EORNE %[result], %[mask], %[result], ASR #31 \n"
619+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
620+
:[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff)
632621
);
633622
return result;
634623
#else
@@ -683,18 +672,15 @@ __inline Word16 div_s (Word16 var1, Word16 var2)
683672
__inline Word16 mult (Word16 var1, Word16 var2)
684673
{
685674
#if ARMV5TE_MULT
686-
Word32 result;
687-
asm volatile(
688-
"SMULBB r2, %[var1], %[var2] \n"
689-
"MOV r3, #1\n"
690-
"MOV %[result], r2, ASR #15\n"
691-
"RSB r3, r3, r3, LSL #15\n"
692-
"MOV r2, %[result], ASR #15\n"
693-
"TEQ r2, %[result], ASR #31\n"
694-
"EORNE %[result], r3, %[result], ASR #31 \n"
695-
:[result]"=r"(result)
696-
:[var1]"r"(var1), [var2]"r"(var2)
697-
:"r2", "r3"
675+
Word32 result, tmp;
676+
asm (
677+
"SMULBB %[tmp], %[var1], %[var2] \n"
678+
"MOV %[result], %[tmp], ASR #15\n"
679+
"MOV %[tmp], %[result], ASR #15\n"
680+
"TEQ %[tmp], %[result], ASR #31\n"
681+
"EORNE %[result], %[mask], %[result], ASR #31 \n"
682+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
683+
:[var1]"r"(var1), [var2]"r"(var2), [mask]"r"(0x7fff)
698684
);
699685
return result;
700686
#else
@@ -719,18 +705,17 @@ __inline Word16 norm_s (Word16 var1)
719705
{
720706
#if ARMV5TE_NORM_S
721707
Word16 result;
722-
asm volatile(
723-
"MOV r2,%[var1] \n"
724-
"CMP r2, #0\n"
725-
"RSBLT %[var1], %[var1], #0 \n"
726-
"CLZNE %[result], %[var1]\n"
708+
Word32 tmp;
709+
asm (
710+
"RSBS %[tmp], %[var1], #0 \n"
711+
"CLZLT %[result], %[var1]\n"
712+
"CLZGT %[result], %[tmp]\n"
727713
"SUBNE %[result], %[result], #17\n"
728714
"MOVEQ %[result], #0\n"
729-
"CMP r2, #-1\n"
715+
"CMP %[var1], #-1\n"
730716
"MOVEQ %[result], #15\n"
731-
:[result]"=r"(result)
717+
:[result]"=&r"(result), [tmp]"=&r"(tmp)
732718
:[var1]"r"(var1)
733-
:"r2"
734719
);
735720
return result;
736721
#else
@@ -979,13 +964,11 @@ __inline Word16 round16(Word32 L_var1)
979964
{
980965
#if ARMV5TE_ROUND
981966
Word16 result;
982-
asm volatile(
983-
"MOV r1,#0x00008000\n"
984-
"QADD %[result], %[L_var1], r1\n"
967+
asm (
968+
"QADD %[result], %[L_var1], %[bias]\n"
985969
"MOV %[result], %[result], ASR #16 \n"
986970
:[result]"=r"(result)
987-
:[L_var1]"r"(L_var1)
988-
:"r1"
971+
:[L_var1]"r"(L_var1), [bias]"r"(0x8000)
989972
);
990973
return result;
991974
#else
@@ -1005,7 +988,7 @@ __inline Word32 L_mac (Word32 L_var3, Word16 var1, Word16 var2)
1005988
{
1006989
#if ARMV5TE_L_MAC
1007990
Word32 result;
1008-
asm volatile(
991+
asm (
1009992
"SMULBB %[result], %[var1], %[var2]\n"
1010993
"QADD %[result], %[result], %[result]\n"
1011994
"QADD %[result], %[result], %[L_var3]\n"
@@ -1029,7 +1012,7 @@ __inline Word32 L_add (Word32 L_var1, Word32 L_var2)
10291012
{
10301013
#if ARMV5TE_L_ADD
10311014
Word32 result;
1032-
asm volatile(
1015+
asm (
10331016
"QADD %[result], %[L_var1], %[L_var2]\n"
10341017
:[result]"=r"(result)
10351018
:[L_var1]"r"(L_var1), [L_var2]"r"(L_var2)

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