Add 8 Verilog IPs to Digital-Verilog-IPs

BIST_FAULT_FREE713/Verilog_files/BIST_FAULT_FREE.V

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+`timescale 1ns / 1ps
+
+module BIST_FAULT_FREE (
+   clk,
+   rst,
+   testmode,
+    in,
+   out,
+    fault_detected,
+   misr_out,
+    complete
+    );
+    input  wire       clk;
+    input  wire       rst;
+    input  wire       testmode;
+    input  wire [3:0] in;
+    output wire [3:0] out;
+    output reg        fault_detected;
+    output wire [3:0] misr_out;
+   output wire complete;
+
+    wire [3:0] mux_out;
+    wire [3:0] lfsr_out;
+    wire [3:0] cut_out;
+
+
+    parameter [3:0] golden_signature = 4'b0011;
+
+    LFSR lfsr_inst (
+        .clk(clk),
+        .rst(rst),
+        .enable(testmode),
+        .lfsr_out(lfsr_out),
+        .complete(complete)
+    );
+
+    MUX mux_inst (
+        .a(in),
+        .b(lfsr_out),
+        .sel(testmode),
+        .out(mux_out)
+    );
+
+    CUT cut_inst (
+        .a(mux_out[3]),
+        .b(mux_out[2]),
+        .c(mux_out[1]),
+        .d(mux_out[0]),
+        .y1(cut_out[3]),
+        .y2(cut_out[2]),
+        .y3(cut_out[1]),
+        .y4(cut_out[0])
+    );
+
+    assign out = cut_out;
+
+    MISR misr_inst (
+        .clk(clk),
+        .reset(rst),
+        .data_in(cut_out),
+        .enable(testmode),
+        .q(misr_out)
+    );
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            fault_detected <= 1'b0;
+        end else if (testmode) begin
+            if (complete) begin
+                fault_detected <= (misr_out != golden_signature);
+            end else begin
+                fault_detected <= 1'b0;
+            end
+        end else begin
+            fault_detected <= 1'b0;
+        end
+    end
+
+endmodule
+
+module LFSR (
+    input  wire       clk,
+    input  wire       rst,
+    input  wire       enable,
+    output reg [3:0]  lfsr_out,
+    output reg        complete
+);
+    reg  [3:0] count;
+    wire feedback;
+
+    assign feedback = lfsr_out[0] ^ lfsr_out[3];
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            lfsr_out <= 4'hF;
+            count    <= 4'b0000;
+            complete <= 1'b0;
+        end 
+        else if (enable) begin
+            lfsr_out <= {lfsr_out[2:0], feedback};
+            count    <= count + 1;
+            if (count == 4'b1111) 
+                complete <= 1'b1;
+            else
+                complete <= 1'b0;
+        end
+    end
+endmodule
+
+module MUX (
+    input  wire [3:0] a,
+    input  wire [3:0] b,
+    input  wire       sel,
+    output wire [3:0] out
+);
+    assign out = sel ? b : a;
+endmodule
+
+module CUT (
+    input  wire a, b, c, d,
+    output wire y1, y2, y3, y4
+);
+
+   wire f0;
+    wire f1, f2, f3, f4;
+    wire sa1 = 1'b1;
+    wire sa0 = 1'b0;
+   or g1(f0,a,b);
+   xor g2(f1,c,d);
+
+   not g3(y1,f0);
+   not g4(y4,f1);
+
+   and g5(y2,f0,f1);
+   or g6(y3,f0,f1);
+
+
+endmodule
+
+module MISR (
+    input        clk,
+    input        reset,
+    input  [3:0] data_in,
+    input        enable,
+    output reg [3:0] q
+);
+    reg feedback;
+
+    always @(posedge clk or posedge reset) begin
+        if (reset) begin
+            q <= 4'b0;
+        end 
+        else if (enable) begin
+            feedback = q[3] ^ data_in[3];
+            q[3] <= q[2] ^ data_in[2];
+            q[2] <= q[1] ^ data_in[1];
+            q[1] <= q[0] ^ data_in[0] ^ feedback;
+            q[0] <= feedback;
+        end
+    end
+endmodule

BIST_FAULT_FREE713/eSim_Test_Circuit_Project_Files/BIST_FAULT_FREE/BIST_FAULT_FREE-cache.lib

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+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_7
+#
+DEF adc_bridge_7 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_7" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -600 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X OUT1 8 550 50 200 L 50 50 1 1 O
+X OUT2 9 550 -50 200 L 50 50 1 1 O
+X OUT3 10 550 -150 200 L 50 50 1 1 O
+X OUT4 11 550 -250 200 L 50 50 1 1 O
+X OUT5 12 550 -350 200 L 50 50 1 1 O
+X OUT6 13 550 -450 200 L 50 50 1 1 O
+X OUT7 14 550 -550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# bist_fault_free
+#
+DEF bist_fault_free U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "bist_fault_free" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 500 0 1 0 N
+X clk0 1 2150 1900 200 R 50 50 1 1 I
+X rst0 2 2150 1800 200 R 50 50 1 1 I
+X testmode0 3 2150 1700 200 R 50 50 1 1 I
+X in3 4 2150 1600 200 R 50 50 1 1 I
+X in2 5 2150 1500 200 R 50 50 1 1 I
+X in1 6 2150 1400 200 R 50 50 1 1 I
+X in0 7 2150 1300 200 R 50 50 1 1 I
+X out3 8 3550 1900 200 L 50 50 1 1 O
+X out2 9 3550 1800 200 L 50 50 1 1 O
+X out1 10 3550 1700 200 L 50 50 1 1 O
+X complete0 20 3550 700 200 L 50 50 1 1 O
+X out0 11 3550 1600 200 L 50 50 1 1 O
+X fault_detected0 12 3550 1500 200 L 50 50 1 1 O
+X misr_out3 13 3550 1400 200 L 50 50 1 1 O
+X misr_out2 14 3550 1300 200 L 50 50 1 1 O
+X misr_out1 15 3550 1200 200 L 50 50 1 1 O
+X misr_out0 16 3550 1100 200 L 50 50 1 1 O
+X complete3 17 3550 1000 200 L 50 50 1 1 O
+X complete2 18 3550 900 200 L 50 50 1 1 O
+X complete1 19 3550 800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_5
+#
+DEF dac_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library