From a561709ff7e28e3d8ae67922068c10754db98164 Mon Sep 17 00:00:00 2001 From: Richard Top Date: Wed, 23 Apr 2025 17:56:04 +0000 Subject: [PATCH 1/7] Add support in archdetect for detecting NVIDIA/Grace --- init/arch_specs/eessi_arch_arm.spec | 1 + .../aarch64/nvidia/grace/Jureca-Rocky95.all.output | 1 + .../aarch64/nvidia/grace/Jureca-Rocky95.cpuinfo | 8 ++++++++ .../archdetect/aarch64/nvidia/grace/Jureca-Rocky95.output | 1 + 4 files changed, 11 insertions(+) create mode 100644 tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.all.output create mode 100644 tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.cpuinfo create mode 100644 tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.output diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index c0d74bd4ad..26cd89e2ec 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -7,3 +7,4 @@ "aarch64/neoverse_n1" "0x41" "asimddp" # AWS Graviton2 "aarch64/neoverse_v1" "ARM" "asimddp svei8mm" "aarch64/neoverse_v1" "0x41" "asimddp svei8mm" # AWS Graviton3 +"aarch64/nvidia/grace" "0x41" "svesm4" # NVIDIA Grace diff --git a/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.all.output b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.all.output new file mode 100644 index 0000000000..9a516a963f --- /dev/null +++ b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.all.output @@ -0,0 +1 @@ +aarch64/nvidia/grace:aarch64/neoverse_v1:aarch64/neoverse_n1:aarch64/generic diff --git a/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.cpuinfo b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.cpuinfo new file mode 100644 index 0000000000..cd5024170f --- /dev/null +++ b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.cpuinfo @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 2000.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd4f +CPU revision : 0 diff --git a/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.output b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.output new file mode 100644 index 0000000000..5878b25414 --- /dev/null +++ b/tests/archdetect/aarch64/nvidia/grace/Jureca-Rocky95.output @@ -0,0 +1 @@ +aarch64/nvidia/grace From 474b02a0616c5af43593dc1f820506e393189aa7 Mon Sep 17 00:00:00 2001 From: Richard Top Date: Thu, 24 Apr 2025 06:10:30 +0000 Subject: [PATCH 2/7] added ssbs CPU feature for detecting NVIDIA/Grace --- init/arch_specs/eessi_arch_arm.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index 26cd89e2ec..b4674248fe 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -7,4 +7,4 @@ "aarch64/neoverse_n1" "0x41" "asimddp" # AWS Graviton2 "aarch64/neoverse_v1" "ARM" "asimddp svei8mm" "aarch64/neoverse_v1" "0x41" "asimddp svei8mm" # AWS Graviton3 -"aarch64/nvidia/grace" "0x41" "svesm4" # NVIDIA Grace +"aarch64/nvidia/grace" "0x41" "ssbs svesm4" # NVIDIA Grace From 9bc946d1b98c8f08bb352ffc7aca0bd2a5122a33 Mon Sep 17 00:00:00 2001 From: Richard Top Date: Thu, 24 Apr 2025 14:30:23 +0000 Subject: [PATCH 3/7] added a valid discriminator between Grace & Axion --- init/arch_specs/eessi_arch_arm.spec | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index b4674248fe..8b63ae30d5 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -7,4 +7,5 @@ "aarch64/neoverse_n1" "0x41" "asimddp" # AWS Graviton2 "aarch64/neoverse_v1" "ARM" "asimddp svei8mm" "aarch64/neoverse_v1" "0x41" "asimddp svei8mm" # AWS Graviton3 -"aarch64/nvidia/grace" "0x41" "ssbs svesm4" # NVIDIA Grace +"aarch64/google/axion" "0x41" "sve2 rng sm3 sm4 svesm4" # Google Axion +"aarch64/nvidia/grace" "0x41" "sve2 sm3 sm4 svesm4" # NVIDIA Grace From 32b6f62e3f606b92228479b5bc7acb211d73fba5 Mon Sep 17 00:00:00 2001 From: TopRichard <121792457+TopRichard@users.noreply.github.com> Date: Thu, 24 Apr 2025 22:55:15 +0200 Subject: [PATCH 4/7] Update init/arch_specs/eessi_arch_arm.spec Co-authored-by: Kenneth Hoste --- init/arch_specs/eessi_arch_arm.spec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index 8b63ae30d5..8b388085bc 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -7,5 +7,5 @@ "aarch64/neoverse_n1" "0x41" "asimddp" # AWS Graviton2 "aarch64/neoverse_v1" "ARM" "asimddp svei8mm" "aarch64/neoverse_v1" "0x41" "asimddp svei8mm" # AWS Graviton3 -"aarch64/google/axion" "0x41" "sve2 rng sm3 sm4 svesm4" # Google Axion "aarch64/nvidia/grace" "0x41" "sve2 sm3 sm4 svesm4" # NVIDIA Grace +"aarch64/google/axion" "0x41" "sve2 rng sm3 sm4 svesm4" # Google Axion From 5fc7a424096782fe684aa5e6eae2b7b7ef717a1c Mon Sep 17 00:00:00 2001 From: Richard Top Date: Fri, 25 Apr 2025 05:53:04 +0000 Subject: [PATCH 5/7] added a comment for the order --- init/arch_specs/eessi_arch_arm.spec | 1 + 1 file changed, 1 insertion(+) diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index 8b388085bc..acba07ff0e 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -1,5 +1,6 @@ # ARM CPU architecture specifications (see https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-socs.html for guidance) # CPU implementers: 0x41 (ARM), 0x46 (Fujitsu) - also see https://github.com/hrw/arm-socs-table/blob/main/data/socs.yml +# Flipping the order of nvidia/grace and google/axion results in nvidia/grace being the "top" on Axion systems # Software path in EESSI | 'Vendor ID' or 'CPU implementer' | List of defining CPU features "aarch64/a64fx" "0x46" "asimdhp sve" # Fujitsu A64FX From f8755ddd1fc30743466f53b41230efd4ec2726f7 Mon Sep 17 00:00:00 2001 From: Kenneth Hoste Date: Fri, 25 Apr 2025 08:42:08 +0200 Subject: [PATCH 6/7] add test case for google/axion + make sure that nvidia/grace test case is also actually used by updating Google Actions workflow --- .github/workflows/tests_archdetect.yml | 2 ++ .../archdetect/aarch64/google/axion/GCP-axion.all.output | 1 + tests/archdetect/aarch64/google/axion/GCP-axion.cpuinfo | 8 ++++++++ tests/archdetect/aarch64/google/axion/GCP-axion.output | 1 + 4 files changed, 12 insertions(+) create mode 100644 tests/archdetect/aarch64/google/axion/GCP-axion.all.output create mode 100644 tests/archdetect/aarch64/google/axion/GCP-axion.cpuinfo create mode 100644 tests/archdetect/aarch64/google/axion/GCP-axion.output diff --git a/.github/workflows/tests_archdetect.yml b/.github/workflows/tests_archdetect.yml index 94fcf68d17..18d08a9023 100644 --- a/.github/workflows/tests_archdetect.yml +++ b/.github/workflows/tests_archdetect.yml @@ -23,6 +23,8 @@ jobs: - aarch64/neoverse_n1/Azure-Ubuntu20-Altra - aarch64/neoverse_n1/AWS-awslinux-graviton2 - aarch64/neoverse_v1/AWS-awslinux-graviton3 + - aarch64/nvidia/grace/Jureca-Rocky95 + - aarch64/google/axion/GCP-axion # commented out since these targets are currently not supported in software.eessi.io repo # (and some tests assume that the corresponding subdirectory in software layer is there) # - ppc64le/power9le/unknown-power9le diff --git a/tests/archdetect/aarch64/google/axion/GCP-axion.all.output b/tests/archdetect/aarch64/google/axion/GCP-axion.all.output new file mode 100644 index 0000000000..66bc16c804 --- /dev/null +++ b/tests/archdetect/aarch64/google/axion/GCP-axion.all.output @@ -0,0 +1 @@ +aarch64/google/axion:aarch64/nvidia/grace:aarch64/neoverse_v1:aarch64/neoverse_n1:aarch64/generic diff --git a/tests/archdetect/aarch64/google/axion/GCP-axion.cpuinfo b/tests/archdetect/aarch64/google/axion/GCP-axion.cpuinfo new file mode 100644 index 0000000000..86924d55f6 --- /dev/null +++ b/tests/archdetect/aarch64/google/axion/GCP-axion.cpuinfo @@ -0,0 +1,8 @@ +processor : 0 +BogoMIPS : 2000.00 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh rng +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x0 +CPU part : 0xd4f +CPU revision : 1 diff --git a/tests/archdetect/aarch64/google/axion/GCP-axion.output b/tests/archdetect/aarch64/google/axion/GCP-axion.output new file mode 100644 index 0000000000..bb5a3a1ee7 --- /dev/null +++ b/tests/archdetect/aarch64/google/axion/GCP-axion.output @@ -0,0 +1 @@ +aarch64/google/axion From c19a1180f1ad87d1c6a88cbdc02d55b4acafa8a6 Mon Sep 17 00:00:00 2001 From: Richard Top Date: Fri, 25 Apr 2025 06:52:49 +0000 Subject: [PATCH 7/7] generalize the comment --- init/arch_specs/eessi_arch_arm.spec | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/init/arch_specs/eessi_arch_arm.spec b/init/arch_specs/eessi_arch_arm.spec index acba07ff0e..5e5e1fd3f2 100755 --- a/init/arch_specs/eessi_arch_arm.spec +++ b/init/arch_specs/eessi_arch_arm.spec @@ -1,6 +1,7 @@ # ARM CPU architecture specifications (see https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-socs.html for guidance) # CPU implementers: 0x41 (ARM), 0x46 (Fujitsu) - also see https://github.com/hrw/arm-socs-table/blob/main/data/socs.yml -# Flipping the order of nvidia/grace and google/axion results in nvidia/grace being the "top" on Axion systems +# To ensure that archdetect produces the correct ordering, CPU targets should be listed from the most specific +# to the most general. In particular, if CPU target A is a subset of CPU target B, then A must be listed before B # Software path in EESSI | 'Vendor ID' or 'CPU implementer' | List of defining CPU features "aarch64/a64fx" "0x46" "asimdhp sve" # Fujitsu A64FX