diff --git a/src/lib.rs b/src/lib.rs index d253c37..c1f364c 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -130,11 +130,15 @@ impl TwoWirePort { mvpdfreq: nvme::mi::SmbusFrequency::FreqNotSupported, cmeaddr: 0x1d, i3csprt: false, - msmbfreq: nvme::mi::SmbusFrequency::Freq400Khz, + msmbfreq: nvme::mi::SmbusFrequency::Freq100Khz, nvmebms: false, smbfreq: nvme::mi::SmbusFrequency::Freq100Khz, } } + + pub fn builder() -> TwoWirePortBuilder { + Default::default() + } } impl Default for TwoWirePort { @@ -143,6 +147,36 @@ impl Default for TwoWirePort { } } +pub struct TwoWirePortBuilder { + msmbfreq: nvme::mi::SmbusFrequency, +} + +impl TwoWirePortBuilder { + pub fn new() -> Self { + Self { + msmbfreq: nvme::mi::SmbusFrequency::Freq100Khz, + } + } + + pub fn msmbfreq(&mut self, freq: nvme::mi::SmbusFrequency) -> &mut Self { + self.msmbfreq = freq; + self + } + + pub fn build(&self) -> TwoWirePort { + TwoWirePort { + msmbfreq: self.msmbfreq, + ..Default::default() + } + } +} + +impl Default for TwoWirePortBuilder { + fn default() -> Self { + Self::new() + } +} + #[derive(Debug, PartialEq, Eq)] #[repr(u8)] pub enum PortType { diff --git a/tests/nvme_mi.rs b/tests/nvme_mi.rs index 3ce4321..9ff8708 100644 --- a/tests/nvme_mi.rs +++ b/tests/nvme_mi.rs @@ -221,7 +221,13 @@ mod read_nvme_mi_data_structure { fn port_information_twowire() { setup(); - let (mut mep, mut subsys) = new_device(DeviceType::P1p1tC1iN0a0a); + let mut subsys = Subsystem::new(SubsystemInfo::invalid()); + let _ = subsys.add_port(PortType::Pcie(PciePort::new())).unwrap(); + let twp = TwoWirePort::builder() + .msmbfreq(nvme_mi_dev::nvme::mi::SmbusFrequency::Freq400Khz) + .build(); + let twpid = subsys.add_port(PortType::TwoWire(twp)).unwrap(); + let mut mep = ManagementEndpoint::new(twpid); #[rustfmt::skip] const REQ: [u8; 19] = [ @@ -1272,7 +1278,13 @@ mod configuration_set { fn smbus_i2c_frequency_supported() { setup(); - let (mut mep, mut subsys) = new_device(DeviceType::P1p1tC1iN0a0a); + let mut subsys = Subsystem::new(SubsystemInfo::invalid()); + let _ = subsys.add_port(PortType::Pcie(PciePort::new())).unwrap(); + let twp = TwoWirePort::builder() + .msmbfreq(nvme_mi_dev::nvme::mi::SmbusFrequency::Freq400Khz) + .build(); + let twpid = subsys.add_port(PortType::TwoWire(twp)).unwrap(); + let mut mep = ManagementEndpoint::new(twpid); #[rustfmt::skip] const REQ_GET_INIT: [u8; 19] = [